- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄382336 > MM54HC4511 (National Semiconductor Corporation) BCD-to-7 Segment Latch/Decoder/Driver PDF資料下載
參數(shù)資料
| 型號(hào)： | MM54HC4511 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | BCD-to-7 Segment Latch/Decoder/Driver |
| 中文描述： | BCD碼至7段鎖存器/解碼器/驅(qū)動(dòng)器 |
| 文件頁(yè)數(shù)： | 4/6頁(yè) |
| 文件大小： | 140K |
| 代理商： | MM54HC4511 |
INPUTS
A, B, C, D (Pins 7, 1, 2, 6)
DBCD data inputs. A (pin 7) is the
least-significant data bit and D (pin 6) is the most significant
bit. Hexadecimal data A–F at these inputs will cause the
outputs to assume a logic low, offering an alternate method
of blanking the display.
OUTPUTS
a–g
DDecoded, buffered outputs. These outputs, unlike the
4511, have CMOS drivers, which will produce typical CMOS
output voltage levels.
CONTROLS
BI (Pin 4)
DActive-low display blanking input. A logic low on
this input will cause all outputs to be held at a logic low,
thereby blanking the display. LT is the only input that will
override the Bl input.
LT (Pin 3)
DActive-low lamp test. A low logic level on this
input causes all outputs to assume a logic high. This input
allows the user to test all segments of a display, with a
single control input. This input is independent of all other
inputs.
LE (Pin 5)
DLatch enable input. This input controls the 4-bit
transparent latch. A logic high on this input latches the data
present at the A, B, C and D inputs; a logic low allows the
data to be transmitted through the latch to the decoder.
Output Characteristics
(V
CC
e
5V)
TL/F/5373–2
*
The expected minimum curves are not guarantees, but are design aids.
TL/F/5373–3
Typical Applications
TL/F/5373–4
Typical Common Cathode LED Connection
TL/F/5373–5
Incandescent Bulb Driving Circuit
4
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MM54HC4511J | BCD-to-7 Segment Latch/Decoder/Driver |
| MM74HC4511J | BCD-to-7 Segment Latch/Decoder/Driver |
| MM74HC4511N | BCD-to-7 Segment Latch/Decoder/Driver |
| MM74HC58J | 1.5A, 520kHz Low Voltage Buck Regulator with External Bias Capability; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98 |
| MM54HC51J | Dual AND-OR-Invert Gate / Dual AND-OR Gate |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM54HC4511 WAF | 制造商:Texas Instruments 功能描述: |
| MM54HC4511E/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MM54HC4511J | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:BCD-to-7 Segment Latch/Decoder/Driver |
| MM54HC4543 WAF | 制造商:Texas Instruments 功能描述: |
| MM54HC51 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Dual AND-OR-Invert Gate / Dual AND-OR Gate |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。