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參數資料
| 型號： | MM54HCT640 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Inverting Octal TRI-STATE Transceiver |
| 中文描述： | 反相八路三態收發器 |
| 文件頁數： | 1/4頁 |
| 文件大?。?/td> | 140K |
| 代理商： | MM54HCT640 |
TL/F/5370
M
M
February 1988
MM54HCT640/MM74HCT640
Inverting Octal TRI-STATE
é
Transceiver
MM54HCT643/MM74HCT643
True-Inverting Octal TRI-STATE Transceiver
General Description
TheseTRI-STATEbi-directionaltransceiversutilizeadvanced
silicon-gate CMOS technology and are intended for two-way
asynchronous communication between data buses. They
have high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits possess the low power consumption of CMOS cir-
cuitry, yet have speeds comparable to low power Schottky
TTL circuits.
All devices are TTL input compatible and can drive up to 15
LS-TTL loads, and all inputs are protected from damage due
to static discharge by diodes to V
CC
and ground.
Both the MM54HCT640/MM74HCT640 and the
MM54HCT643/ MM74HCT643 have one active low enable
input (G), and a direction control (DIR). When the DIR input
is high, data flows from the A inputs to the B outputs. When
DIR is low, data flows from B to A. The MM54HCT640/
MM74HCT640 transfers inverted data from one bus to the
other. The MM54HCT643/MM74HCT643 transfers inverted
data from the A bus to the B bus and non-inverted data from
the B bus to the A bus.
MM54HCT/MM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs.
Features
Y
TTL input compatible
Y
Octal TRI-STATE outputs for
m
P bus applications:
6 mA, typical
Y
High speed: 16 ns typical propagation delay
Y
Low power: 80
m
A maximum (74HCT)
Connection Diagram
Dual-In-Line Packages
TL/F/5370–1
Top View
Order Number MM54HCT640 or MM74HCT640
TL/F/5370–2
Top View
Order Number MM54HCT643 or MM74HCT643
Truth Table
Control
Inputs
Operation
G
DIR
640
643
L
L
B data to A bus
B data to A bus
L
H
A data to B bus
A data to B bus
H
X
Isolation
Isolation
H
e
high level, L
e
low level, X
e
irrelevant
TRI-STATE
é
is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
相關PDF資料 |
PDF描述 |
|---|---|
| MM54HCT640J | Inverting Octal TRI-STATE Transceiver |
| MM54HCT643J | Inverting Octal TRI-STATE Transceiver |
| MM74HCT640 | Inverting Octal TRI-STATE Transceiver |
| MM74HCT640J | Inverting Octal TRI-STATE Transceiver |
| MM74HCT640N | Inverting Octal TRI-STATE Transceiver |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MM54HCT640J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM54HCT643 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM54HCT643J | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Inverting Octal TRI-STATE Transceiver |
| MM54HCT688 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit Magnitude Comparator (Equality Detector) |
| MM54HCT74 WAF | 制造商:Texas Instruments 功能描述: |
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