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參數(shù)資料
| 型號(hào)： | MM58167BV |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Microprocessor Real Time Clock |
| 中文描述： | 0 TIMER(S), REAL TIME CLOCK, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁(yè)數(shù)： | 3/10頁(yè) |
| 文件大小： | 173K |
| 代理商： | MM58167BV |
Functional Description
Real Time Counter
The real time counter is divided into 4-bit digits with 2 digits
being accessed during any read or write cycle. Each digit
represents a BCD number and is defined in Table I. Any
unused bits are held at a logical zero during a read and
ignored during a write. An unused bit is any bit not neces-
sary to provide a full BCD number. For example tens of
hours cannot legally exceed the number 2, thus only 2 bits
are necessary to define the tens of hours. The other 2 bits in
the tens of hours digit are unused. The unused bits are des-
ignated in Table I as dashes.
The addressable portion of the counter is from milliseconds
to months. The counter itself is a ripple counter. The ripple
delay is less than 60
m
s above 4.5V and 300
m
s at 2.2V.
RAM
56 bits of RAM are contained on-chip. These can be used
for any necessary power down storage or as an alarm latch
for comparison to the real time counter. The data in the
RAM can be compared to the real time counter on a digit
basis. The only digits that are not compared are the unit ten
thousandths of seconds and tens of days of the week
(these are unused in the real time counter). If the two most
significant bits of any RAM digit are ones, then this RAM
location will always compare. The rule of thumb for an
‘‘a(chǎn)larm’’ interrupt is: All nibbles of higher order than speci-
fied are set to C hex (always compare). All nibbles lower
than specified are set to ‘‘zero’’. As an example, if an alarm
is to occur everyday at 10:15 a.m., configure the bits in RAM
as shown in Table II.
The RAM is formatted the same as the real time counter, 4
bits per digit, 14 digits, however there are no unused bits.
The unused bits in the real time counter will compare only to
zeros in the RAM.
An address map is shown in Table III.
Interrupts and Comparator
There are two interrupt outputs. The first is the INTERRUPT
OUTPUT (a true high signal). This output can be pro-
grammed to provide 8 different output signals. They are:
10 Hz, once per second, once per minute, once per hour,
once a day, once a week, once a month, and when a RAM/
real time counter comparison occurs. To enable the output
a one is written into the interrupt control register at the bit
location corresponding to the desired output frequency (Fig-
ure 1). Once one or more bits have been set in the interrupt
control register, the corresponding counter’s rollover to its
reset state will clock the interrupt status register and cause
the interrupt output to go high. To reset the interrupt and to
identify which frequency caused the interrupt, the interrupt
status register is read. Reading this register places the con-
tents of the status register on the data bus. The interrupting
frequency will be identified by a one in the respective bit
position. Removing the read will reset the interrupt.
The second interrupt is the STANDBY INTERRUPT (open
drain output, active low). This interrupt occurs when enabled
and when a RAM/real time counter comparison occurs. The
STANDBY INTERRUPT is enabled by writing a one on the
D0 line at address 16
H
or disabled by writing a zero on the
D0 line. This interrupt is not triggered by the edge of the
compare signal, but rather by the level. Thus if the compare
is enabled when the STANDBY INTERRUPT is enabled, the
interrupt will turn on immediately.
TABLE I. Real Time Counter Format
Units
Max
BCD
Code
Tens
Max
BCD
Code
Counter Addressed
D0
D1
D2
D3
D4
D5
D6
D7
Milliseconds
Hundredths and Tenths Sec
Seconds
Minutes
Hours
Day of the Week
Day of the Month
Month
(00
H
)
(01
H
)
(02
H
)
(03
H
)
(04
H
)
(05
H
)
(06
H
)
(07
H
)
D
D0
D0
D0
D0
D0
D0
D0
D
D1
D1
D1
D1
D1
D1
D1
D
D2
D2
D2
D2
D2
D2
D2
D
D3
D3
D3
D3
D
D3
D3
0
9
9
9
9
7
9
9
D4
D4
D4
D4
D4
D
D4
D4
D5
D5
D5
D5
D5
D
D5
D
D6
D6
D6
D6
D
D
D
D
D7
D7
D
D
D
D
D
D
9
9
5
5
2
0
3
1
(D) indicates unused bits
3
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相關(guān)代理商/技術(shù)參數(shù) |
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