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參數資料
| 型號： | MM74C95J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 4-Bit Right-Shift Left-Shift Register |
| 中文描述： | CMOS SERIES, 4-BIT RIGHT PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDIP14 |
| 封裝： | CERAMIC, DIP-14 |
| 文件頁數： | 3/4頁 |
| 文件大小： | 108K |
| 代理商： | MM74C95J |
AC Electrical Characteristics
*
T
A
e
25
§
C, C
L
e
50 pF, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
t
pd
Propagation Delay Time to a Logical
‘‘0’’ or Logical ‘‘1’’ from Clock to Q or Q
V
CC
e
5V
V
CC
e
10V
200
80
400
160
ns
ns
t
S0
, t
S1
Time Prior to Clock Pulse that Data
must be Preset
V
CC
e
5V
V
CC
e
10V
60
25
30
10
ns
ns
t
H0
, t
H1
Time After Clock Pulse that Data
must be Held
V
CC
e
5V
V
CC
e
10V
25
10
10
50
ns
ns
t
PW
Minimum Clock Pulse Width (t
WL
e
t
WH
)
V
CC
e
5V
V
CC
e
10V
100
50
ns
ns
t
SM
Time Prior to Clock Pulse that Mode
Control must be Preset
V
CC
e
5V
V
CC
e
10V
200
100
100
50
ns
ns
f
MAX
Maximum Input Clock Frequency
V
CC
e
5V
V
CC
e
10V
3
5
MHz
MHz
6.5
10
C
IN
Input Capacitance
Any Input (Note 2)
5
pF
C
PD
*
AC Parameters are guaranteed by DC correlated testing.
Power Dissipation Capacitance
(Note 3)
100
pF
Note 1:
‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’,
they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device
operation.
Note 2:
Capacitance is guaranteed by periodic testing.
Note 3:
C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C/74C Family Characteristics, Application Note
AN-90.
Function Table
Inputs
Outputs
Mode
Control
Clocks
Serial
Parallel
Q
A
Q
B
Q
C
Q
D
2 (L)
1 (R)
A
B
C
D
H
H
H
L
L
L
u
v
v
u
u
u
v
H
v
v
L
X
X
L
L
L
H
H
L
H
X
X
X
H
v
v
L
L
H
L
H
H
L
X
X
X
X
H
L
X
X
X
X
X
X
X
X
a
X
b
X
c
X
c
d
X
X
X
X
X
X
X
X
X
X
Q
A0
a
Q
Bn
Q
A0
H
L
Q
A0
Q
A0
Q
A0
Q
A0
Q
A0
Undefined
Operating Conditions
Q
B0
b
Q
Cn
Q
B0
Q
An
Q
An
Q
B0
Q
B0
Q
B0
Q
B0
Q
B0
Q
C0
c
Q
Dn
Q
C0
Q
Bn
Q
Bn
Q
C0
Q
C0
Q
C0
Q
C0
Q
C0
Q
D0
d
d
Q
D0
Q
Cn
Q
Cn
Q
D0
Q
D0
Q
D0
Q
D0
Q
D0
Q
B
2
X
X
X
X
X
X
X
X
X
X
Q
C
2
X
X
X
X
X
X
X
X
X
X
Q
D
2
X
X
X
X
X
X
X
X
X
X
2
Shifting left requires external connection of Q
B
to A, Q
C
to B, and Q
D
to C. Serial data is entered at input D.
H
e
high level (steady state), L
e
low level (steady state), X
e
irrelevant (any input, including transitions)
v
e
transition from high to low level,
u
e
transition from low to high level.
a, b, c, d
e
the level of steady-state input at inputs A, B, C or D, respectively.
Q
A0
, Q
B0
, Q
C0
, Q
D0
e
the level of Q
A
, Q
B
, Q
C
or Q
D
respectively, before the indicated steady-state input conditions
were established.
Q
An
, Q
Bn
, Q
Cn
, Q
Dn
e
the level of Q
A
, Q
B
, Q
C
or Q
D
respectively, before the most recent transition of the clock.
3
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