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參數資料
| 型號： | MM74HC194 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 4-Bit Bidirectional Universal Shift Register |
| 中文描述： | 4位雙向通用移位寄存器 |
| 文件頁數： | 3/6頁 |
| 文件大小： | 135K |
| 代理商： | MM74HC194 |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
f
MAX
Maximum Operating
Frequency
50
35
MHz
t
PHL
, t
PLH
Maximum Propagation
Delay, Clock to Q
17
24
ns
t
PHL
Maximum Propagation
Delay, Reset to Q
19
25
ns
t
REM
Minimum Removal Time,
Reset Inactive to Clock
5
ns
t
S
Minimum Setup Time
(A, B, C, D to Clock)
20
ns
t
S
Minimum Setup Time
Mode Controls to Clock
20
ns
t
W
Minimum Pulse Width
Clock or Reset
9
16
ns
t
H
Minimum Hold Time
any Input
b
3
0
ns
AC Electrical Characteristics
C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
Guaranteed Limits
T
A
eb
55 to 125
§
C
Units
Typ
f
MAX
Maximum Operating
Frequency
2.0V
4.5V
6.0V
10
45
50
6
5
4
30
35
24
28
20
24
MHz
MHz
t
PHL
, t
PLH
Maximum Propagation
Delay, Clock to Q
2.0V
4.5V
6.0V
70
15
12
145
29
25
183
37
31
216
45
37
ns
ns
ns
t
PHL
Maximum Propagation
Delay, Reset to Q
2.0V
4.5V
6.0V
80
15
12
150
30
26
189
37
31
216
45
37
ns
ns
ns
t
THL
, t
TLH
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
7
75
15
13
95
19
16
110
22
19
ns
ns
ns
t
REM
Minimum Removal Time
Reset Inactive to Clock
2.0V
4.5V
6.0V
5
5
5
5
5
5
5
5
5
ns
ns
ns
t
S
Minimum Set Up Time
(A, B, C, or D to Clock)
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
t
S
Minimum Set Time
Mode Controls to Clock
2.0V
4.5V
6.0V
100
20
17
125
25
21
150
30
25
ns
ns
ns
t
H
Minimum Hold Time
any Input
2.0V
4.5V
6.0V
b
10
b
3
b
3
30
89
8
0
0
0
0
0
0
0
0
0
ns
ns
ns
t
W
Minimum Pulse Width
Clock or Reset
2.0V
4.5V
6.0V
80
16
14
100
20
18
120
24
20
ns
ns
ns
t
r
, t
f
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
C
PD
Power Dissipation
Capacitance (Note 5)
77
pF
C
IN
Maximum Input
Capacitance
5
10
10
10
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
3
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