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參數資料
| 型號： | MM74HC373MTCX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LATCH OCTAL D 3ST 20TSSOP |
| 標準包裝： | 1 |
| 系列： | 74HC |
| 邏輯類型： | D 型透明鎖存器 |
| 電路： | 8:8 |
| 輸出類型： | 三態 |
| 電源電壓： | 2 V ~ 6 V |
| 獨立電路： | 1 |
| 延遲時間 - 傳輸： | 19ns |
| 輸出電流高，低： | 7.8mA，7.8mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 20-TSSOP |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 1209 (CN2011-ZH PDF) |
| 其它名稱： | MM74HC373MTCXDKR |
2005 Fairchild Semiconductor Corporation
DS005335
www.fairchildsemi.com
September 1983
Revised May 2005
MM74HC373
3-ST
A
T
E
Oct
a
lD-
T
ype
L
a
tch
MM74HC373
3-STATE Octal D-Type Latch
General Description
The MM74HC373 high speed octal D-type latches utilize
advanced silicon-gate CMOS technology. They possess
the high noise immunity and low power consumption of
standard CMOS integrated circuits, as well as the ability to
drive 15 LS-TTL loads. Due to the large output drive capa-
bility and the 3-STATE feature, these devices are ideally
suited for interfacing with bus lines in a bus organized sys-
tem.
When the LATCH ENABLE input is HIGH, the Q outputs
will follow the D inputs. When the LATCH ENABLE goes
LOW, data at the D inputs will be retained at the outputs
until LATCH ENABLE returns HIGH again. When a high
logic level is applied to the OUTPUT CONTROL input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pin-out com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s Typical propagation delay: 18 ns
s Wide operating voltage range: 2 to 6 volts
s Low input current: 1
PA maximum
s Low quiescent current: 80
PA maximum (74 Series)
s Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
H
HIGH Level
L
LOW Level
Q0 Level of output before steady-state input conditions were established.
Z
High Impedance
Order Number
Package Number
Package Description
MM74HC373WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC373SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC373MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC373N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Output
Latch
Data
373
Control
Enable
Output
L
HHH
LH
L
LL
X
Q0
HX
X
Z
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MM74HC373MTCX-CUT TAPE | 制造商:FAIRCHILD 功能描述:MM74HC Series High Speed CMOS 3-STATE Octal D-Type Latch - TSSOP-20 |
| MM74HC373N | 功能描述:閉鎖 3-STATE Oct D Latch RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| MM74HC373N | 制造商:Fairchild Semiconductor Corporation 功能描述:IC FLIP-FLOPS LOGIC ROHS COMPLIANT:NO |
| MM74HC373N | 制造商:Fairchild Semiconductor Corporation 功能描述:IC 74HC CMOS 74HC373 DIP20 6V |
| MM74HC373N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit D-Type Latch |
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