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參數(shù)資料
| 型號： | MM74HC4511 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | BCD-to-7 Segment Latch/Decoder/Driver |
| 中文描述： | BCD碼至7段鎖存器/解碼器/驅(qū)動器 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大小： | 140K |
| 代理商： | MM74HC4511 |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
t
PHL
, t
PLH
Maximum Propagation
Delay from Inputs A thru D to any Output
60
120
ns
t
PHL
, t
PLH
Maximum Propagation
Delay from BI to any Output
60
120
ns
t
PHL
, t
PLH
Maximum Propagation
Delay from LT to any Output
60
120
ns
t
S
Minimum Setup Time
Inputs A thru D to LE
10
20
ns
t
H
Minimum Hold Time
Inputs A thru D to LE
b
3
0
ns
t
W
Minimum Pulse Width
for LE
16
ns
AC Electrical Characteristics
C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HC
54HC
Symbol
Parameter
Conditions
V
CC
T
A
eb
40 to 85
§
C
T
A
eb
55 to 125
§
C
Units
Typ
Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation
Delay from Inputs
A thru D to any Output
LE
e
0V
LT
e
V
CC
BI
e
V
CC
2.0V
4.5V
6.0V
300
60
51
600
120
102
756
151
129
894
179
152
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay from BI to
any Output
LT
e
V
CC
2.0V
4.5V
6.0V
300
60
51
600
120
102
756
151
129
894
179
152
ns
ns
ns
t
PHL
, t
PLH
Maximum Propagation
Delay from LT to
any Output
BI
e
0V
2.0V
4.5V
6.0V
300
60
51
600
120
102
756
151
129
894
179
152
ns
ns
ns
t
S
Minimum Setup Time
Inputs A thru D to LE
2.0V
4.5V
6.0V
100
20
17
126
25
21
149
30
25
ns
ns
ns
t
H
Minimum Hold Time
Inputs A thru D to LE
2.0V
4.5V
6.0V
0
0
0
0
0
0
0
0
0
ns
ns
ns
t
W
Minimum Pulse Width
for LE
2.0V
4.5V
6.0V
80
16
14
100
20
17
120
24
20
ns
ns
ns
t
r
, t
f
Maximum Input Rise and
Fall Time
2.0V
4.5V
6.0V
1000
500
400
1000
500
400
1000
500
400
ns
ns
ns
C
PD
Power Dissipation
Capacitance (Note 5)
pF
C
IN
Maximum Input
Capacitance
5
10
10
10
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
3
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