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參數資料
| 型號： | MM74HC573WMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 1/8頁 |
| 文件大小： | 0K |
| 描述： | IC LATCH OCTAL D 3STATE 20-SOIC |
| 標準包裝： | 1 |
| 系列： | 74HC |
| 邏輯類型： | D 型透明鎖存器 |
| 電路： | 8:8 |
| 輸出類型： | 三態 |
| 電源電壓： | 2 V ~ 6 V |
| 獨立電路： | 1 |
| 延遲時間 - 傳輸： | 15ns |
| 輸出電流高，低： | 7.8mA，7.8mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 1209 (CN2011-ZH PDF) |
| 其它名稱： | MM74HC573WMXDKR |
2005 Fairchild Semiconductor Corporation
DS005212
www.fairchildsemi.com
September 1983
Revised May 2005
MM74HC573
3-ST
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T
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Oct
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ype
L
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MM74HC573
3-STATE Octal D-Type Latch
General Description
The MM74HC573 high speed octal D-type latches utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
When the LATCH ENABLE(LE) input is HIGH, the Q out-
puts will follow the D inputs. When the LATCH ENABLE
goes LOW, data at the D inputs will be retained at the out-
puts until LATCH ENABLE returns HIGH again. When a
HIGH logic level is applied to the OUTPUT CONTROL OC
input, all outputs go to a HIGH impedance state, regardless
of what signals are present at the other inputs and the state
of the storage elements.
The 74HC logic family is speed, function and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s Typical propagation delay: 18 ns
s Wide operating voltage range: 2 to 6 volts
s Low input current: 1
PA maximum
s Low quiescent current: 80
PA maximum (74HC Series)
s Compatible with bus-oriented systems
s Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Top View
Truth Table
H
HIGH Level
L
LOW Level
Q0
Level of output before steady-state input conditions were established.
Z
High Impedance
X
Don't Care
Order Number
Package Number
Package Description
MM74HC573WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC573N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Output
Latch
Data
Output
Control
Enable
L
HHH
LH
L
LL
X
Q0
HX
X
Z
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MM74HC573WMX_NL | 制造商:Fairchild Semiconductor Corporation 功能描述:3-STATE OCTAL D-TYPE LATCH |
| MM74HC573WMX-CUT TAPE | 制造商:FAIRCHILD 功能描述:MM74HC Series High Speed CMOS 3-STATE Octal D-Type Latch - SOIC-20 |
| MM74HC574 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:3-STATE Octal D-Type Edge-Triggered Flip-Flop |
| MM74HC574J | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Octal D-Type Flip-Flop |
| MM74HC574J/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Octal D-Type Flip-Flop |
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