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參數資料
| 型號： | MM74HC574WMX |
| 廠商： | Fairchild Semiconductor |
| 文件頁數： | 1/8頁 |
| 文件大小： | 0K |
| 描述： | IC FLIP FLOP OCT D 3ST 20-SOIC |
| 標準包裝： | 1 |
| 系列： | 74HC |
| 功能： | 標準 |
| 類型： | D 型總線 |
| 輸出類型： | 三態非反相 |
| 元件數： | 1 |
| 每個元件的位元數： | 8 |
| 頻率 - 時鐘： | 35MHz |
| 延遲時間 - 傳輸： | 18ns |
| 觸發器類型： | 正邊沿 |
| 輸出電流高，低： | 7.8mA，7.8mA |
| 電源電壓： | 2 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 包裝： | 標準包裝 |
| 其它名稱： | MM74HC574WMXDKR |
2005 Fairchild Semiconductor Corporation
DS005213
www.fairchildsemi.com
September 1983
Revised May 2005
MM74HC574
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MM74HC574
3-STATE Octal D-Type Edge-Triggered Flip-Flop
General Description
The MM74HC574 high speed octal D-type flip-flops utilize
advanced silicon-gate P-well CMOS technology. They pos-
sess the high noise immunity and low power consumption
of standard CMOS integrated circuits, as well as the ability
to drive 15 LS-TTL loads. Due to the large output drive
capability and the 3-STATE feature, these devices are ide-
ally suited for interfacing with bus lines in a bus organized
system.
These devices are positive edge triggered flip-flops. Data
at the D inputs, meeting the set-up and hold time require-
ments, are transferred to the Q outputs on positive going
transitions of the CLOCK (CK) input. When a high logic
level is applied to the OUTPUT CONTROL (OC) input, all
outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the
storage elements.
The 74HC logic family is speed, function, and pinout com-
patible with the standard 74LS logic family. All inputs are
protected from damage due to static discharge by internal
diode clamps to VCC and ground.
Features
s Typical propagation delay: 18 ns
s Wide operating voltage range: 2V–6V
s Low input current: 1
PA maximum
s Low quiescent current: 80
PA maximum
s Compatible with bus-oriented systems
s Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
H
HIGH Level
L
LOW Level
X
Don't Care
n Transition from LOW-to-HIGH
Z
High Impedance State
Q0
The level of the output before steady state input conditions were
established
Order Number
Package Number
Package Description
MM74HC574WM
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC574SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC574MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC574N
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Output
Clock
Data
Output
Control
L
n
HH
L
n
LL
X
Q0
HX
X
Z
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