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參數資料
型號: MM74HCT00SJX
廠商: Fairchild Semiconductor
文件頁數: 1/9頁
文件大小: 0K
描述: IC GATE NAND QUAD 2-INP 14-SOP
標準包裝: 2,000
系列: 74HCT
邏輯類型: 與非門
電路數: 4
輸入數: 2
電源電壓: 4.5 V ~ 5.5 V
電流 - 靜態(最大值): 1µA
輸出電流高,低: 4.8mA,4.8mA
邏輯電平 - 低: 0.8V
邏輯電平 - 高: 2V
額定電壓和最大 CL 時的最大傳播延遲: 23ns @ 5V,50pF
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
供應商設備封裝: 14-SOIC
封裝/外殼: 14-SOIC(0.209",5.30mm 寬)
包裝: 帶卷 (TR)
MM74HCT00
Quad
2
Input
NAND
Gate
1984 Fairchild Semiconductor Corporation
www.fairchildsemi.com
MM74HCT00 Rev. 1.3.0
February 2008
MM74HCT00
Quad 2 Input NAND Gate
Features
TTL, LS pin-out and threshold compatible
Fast switching: tPLH, tPHL=14ns (typ.)
Low power: 10W at DC
High fan out, 10 LS-TTL loads
General Description
The MM74HCT00 is a NAND gates fabricated using
advanced silicon-gate CMOS technology which provides
the inherent benefits of CMOS—low quiescent power
and wide power supply range. This device is input and
output characteristic and pin-out compatible with stan-
dard 74LS logic families. All inputs are protected from
static discharge damage by internal diodes to VCC and
ground.
MM74HCT devices are intended to interface between
TTL and NMOS components and standard CMOS
devices. These parts are also plug-in replacements for
LS-TTL devices and can be used to reduce power
consumption in existing designs.
Ordering InformationOrdering Information
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Logic Diagram
(1 of 4 gates)
Order Number
Package
Number
Package Description
MM74HCT00M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HCT00SJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT00MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT00N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
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