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參數(shù)資料
| 型號： | MM74HCT109J |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | Dual J-K Flip-Flops with Preset and Clear |
| 中文描述： | HCT SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, CDIP16 |
| 封裝： | DIP-16 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 123K |
| 代理商： | MM74HCT109J |
AC Electrical Characteristics
V
CC
e
5V, T
A
e
25
§
C, C
L
e
15 pF, t
r
e
t
f
e
6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
f
MAX
Maximum Operating
Frequency
50
30
MHz
t
PHL
, t
PLH
Maximum Propagation
Delay from Clock to Q or Q
18
30
ns
t
PHL
, t
PLH
Maximum Propagation
Delay from Preset or Clear to Q or Q
18
30
ns
t
REM
Minimum Removal Time,
Preset or Clear to Clock
20
ns
t
S
Minimum Setup Time
J or K Clock
10
20
ns
t
H
Minimum Hold Time
Clock to J or K
b
3
0
ns
t
W
Minimum Pulse Width
Clock, Preset or Clear
8
16
ns
AC Electrical Characteristics
V
CC
e
5.0V
g
10%, C
L
e
50 pF, t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25
§
C
74HCT
54HCT
Symbol
Parameter
Conditions
T
A
eb
40
§
to 85
§
C
T
A
eb
55
§
to 125
§
C
Units
Typ
Guaranteed Limits
f
MAX
Maximum Operating
Frequency
27
22
18
MHz
t
PHL
, t
PLH
Maximum Propagation
Delay from Clock to
Q or Q
22
35
44
52
ns
t
PHL
, t
PLH
Maximum Propagation
Delay from Preset
or Clear to Q or Q
22
35
44
52
ns
t
REM
Minimum Removal Time
Preset or Clear to Clock
20
25
30
ns
t
S
Minimum Setup Time
J or K to Clock
10
20
25
30
ns
t
H
Minimum Hold Time
Clock to J or K
b
3
0
0
0
ns
t
W
Minimum Pulse Width
Clock, Preset or Clear
16
20
24
ns
t
r
, t
f
Maximum Input Rise and
Fall Time
500
500
500
ns
t
THL
, t
TLH
Maximum Output
Rise and Fall Time
15
19
22
ns
C
PD
Power Dissipation
Capacitance (Note 5)
(per flip-flop)
35
pF
C
IN
Maximum Input
Capacitance
5
10
10
10
pF
Note 5:
C
PD
determines the no load dynamic power consumption, P
D
e
C
PD
V
CC2
f
a
I
CC
V
CC
, and the no load dynamic current consumption, I
S
e
C
PD
V
CC
f
a
I
CC
.
3
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