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參數(shù)資料
| 型號： | MM74HCT138N |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 編、解碼器及復用、解復用 |
| 英文描述： | HC/UH SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, PDIP16 |
| 封裝： | DIP-16 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 116K |
| 代理商： | MM74HCT138N |
TLF5362
MM54HCT138MM74HCT138
3-to-8
Line
Decoder
January 1988
MM54HCT138MM74HCT138
3-to-8 Line Decoder
General Description
This decoder utilizes advanced silicon-gate CMOS technol-
ogy and are well suited to memory address decoding or
data routing applications Both circuits feature high noise
immunity and low power consumption usually associated
with CMOS circuitry yet have speeds comparable to low
power Schottky TTL logic
The MM54HCT138MM74HCT138 have 3 binary select in-
puts (A B and C) If the device is enabled these inputs
determine which one of the eight normally high outputs will
go low Two active low and one active high enables (G1
G2A and G2B) are provided to ease the cascading de-
coders
The decoders’ output can drive 10 low power Schottky TTL
equivalent loads and are functionally and pin equivalent to
the 54LS13874LS138 All inputs are protected from dam-
age due to static discharge by diodes to VCC and ground
MM54HCTMM74HCT devices are intended to interface be-
tween TTL and NMOS components and standard CMOS
devices These parts are also plug-in replacements for LS-
TTL devices and can be used to reduce power consumption
in existing designs
Features
Y
TTL input compatible
Y
Typical propagation delay 20 ns
Y
Low quiescent current 80 mA maximum (74HCT Series)
Y
Low input current 1 mA maximum
Y
Fanout of 10 LS-TTL loads
Connection Diagram
Dual-In-Line Package
TLF5362 – 1
Order Number MM54HCT138
or MM74HCT138
Logic Diagram
TLF5362–2
Truth Table
Inputs
Outputs
Enable
Select
G1 G2
C B AY0Y1Y2Y3Y4Y5Y6Y7
X
H
X
HHHHHHHH
L
X
HHHHHHHH
H
L
HHHHHHH
H
L
H
L
H
HHHHH
H
L
H
L
H
L
H
HHHH
H
L
H H
HHH
L
HHHH
H
L
H
L
HHHH
L
HHH
H
L
H
L
H
HHHHH
L
H
L
H H
L
HHHHHH
L
H
L
H H H
HHHHHHH
L
G2 e G2A a G2B
H e high level L e low level X e don’t care
C1995 National Semiconductor Corporation
RRD-B30M105Printed in U S A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MM74HCT138N | 制造商:Fairchild Semiconductor Corporation 功能描述:74HCT CMOS 74HCT138 DIP16 5.5V |
| MM74HCT138N/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-To-8-Line Demultiplexer |
| MM74HCT138N/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-To-8-Line Demultiplexer |
| MM74HCT138N_Q | 功能描述:編碼器、解碼器、復用器和解復用器 3-to-8 Line Decoder RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
| MM74HCT138SJ | 功能描述:編碼器、解碼器、復用器和解復用器 3-to-8 Line Decoder RoHS:否 制造商:Micrel 產(chǎn)品:Multiplexers 邏輯系列:CMOS 位數(shù): 線路數(shù)量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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