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參數(shù)資料
| 型號(hào)： | MN3308 |
| 廠商： | PANASONIC CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 2048-Stage Ultra Low Voltage Operation BBD for Audio Signals |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP8 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件頁(yè)數(shù)： | 1/5頁(yè) |
| 文件大小： | 55K |
| 代理商： | MN3308 |
MN3300 Series
MN3308
2048-Stage Ultra Low Voltage Operation BBD for Audio Signals
1
I
Overview
The MN3308 is a 2048-stage ultra low voltage operation BBD
variable delay line in audio frequency range. The device operates on
+
3 V supply and provides a signal delay up to 102.4 ms and is suitable
for use as reverberation effect of low voltage operation audio equip-
ment such as portable stereo, radio cassette recorder and microphone.
I
Features
Variable signal delay of the audio signal : 3.42 to 102.4 ms
Wide range of supply voltage : 1.8 to 7.0 V
No insertion loss : L
i
=
0 dB typ.
Wide dynamic range : S/N
=
66 dB typ.
Clock frequency range :10 to 100 kHz (1.8 V
≤
V
DD
<
4.0 V)
10 to 300 kHz (4.0 V
≤
V
DD
≤
7.0 V)
N-channel 2-layer silicon gate process
8-Pin Dual-In-Line Plastic Package
I
Applications
Reverberation and echo effects of audio equipment such as radio
cassette recorder, car radio, portable radio, portable stereo, echo
microphone and Karaoke machine, etc.
Sound effect of electronic musical instruments
Variable or fixed delay of analog signals
DIP008-P-0300
Pin No.
Symbol
Pin Name
Description
1
GND
Ground pin
Connected to ground.
2
CP2
Clock input 2
Basic clock pulse is applied to transfer electric charge of BBD.
3
4
IN
V
DD
Signal input pin
V
DD
apply pin
Analog signal to be delayed is input. Most suitable DC bias should be applied to this pin.
Bias is applied to the gate of MOS transistor which is inserted in series with clock pulse
input gate of the BBD transfer gate.
Furthermore, voltage is supplied to step-up circuit.
5
V
D1
CP1
V
D1
apply pin
Clock input 1
The same phase clock pulse as CP1 is applied through capacitor.
6
Clock pulse of inverted phase to CP2 is applied.
7
OUT
Output pin
Composed signal of 1024th and 1025th stages is output.
8
V
D2
V
D2
apply pin
The same phase clock pulse as CP2 is applied through capacitor.
I
Pin Descriptions
I
Pin Assignment
2048-Stage
BBD
8
7
IN
3
V
D2
OUT
V
D1
5
4
1
C
C
6
2
V
D
G
I
Block Diagram
1
2
MN3308
3
4
V
D2
OUT
CP1
V
D1
GND
CP2
IN
V
DD
8
7
6
5
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