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參數資料
| 型號： | MN61113S |
| 廠商： | PANASONIC CORP |
| 元件分類： | DRAM |
| 英文描述： | 2K-Bit EEPROMs |
| 中文描述： | 2K X 1 EEPROM 3V, PDSO8 |
| 封裝： | 0.225 INCH, PLASTIC, SOP-8 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 45K |
| 代理商： | MN61113S |
1
EEPROMs
MN61113, MN61113S
2K-Bit EEPROMs
Overview
The MN61113 and MN61113S are 2048-bit, bit sequen-
tial EEPROMs with built-in address counters. They se-
quentially increment the address with the clock input to
produce serial output.
They include built-in charge pump circuit and timer for
automatically erasing, writing, and modifying data using
only a single 3 volt power supply.
To reduce write times, they include a block write func-
tion for writing up to 32 bits at a time. This function makes
it possible to rewrite the contents of all 2048 bits within
1 second (typ.).
Features
2048 words
×
1 bit organization
Built-in reset function
Tristate output
Low power consumption
3 volt read: 1.5 mW (max.)
3 volt program: 6 mW (max.)
3 volt standby: 60
μ
W (max.)
Single 3 volt power supply (charge pump circuit
built in)
Self timer for use in automatically erasing and
writing data
Built-in data polling function
Write cycles: 10
5
times
Data storage interval: 10 years
Pull-up resistor on CE pin.
Pull-down resistors on PGM, CLK, and RST pins
Applications
Personal wireless equipment, cordless telephones,
storage for recognition and adjustment data for
terminals, etc.
Pin Assignment
(TOP VIEW)
MN61113
MN61113S
DIP008-P-0300A
SOP008-P-0225
1
2
3
4
DATA
CE
V
CC
GND
8
7
6
5
OE
RST
CLK
PGM
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