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參數資料
| 型號： | MPC9315ACR2 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9315 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 401K |
| 代理商： | MPC9315ACR2 |
MPC9315
Rev. 4, 08/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
2.5 V and 3.3 V CMOS PLL Clock
Generator and Driver
The MPC9315 is a 2.5 V and 3.3 V compatible, PLL based clock generator
designed for low-skew clock distribution in low-voltage mid-range to
high-performance telecom, networking and computing applications. The
MPC9315 offers 8 low-skew outputs and 2 selectable inputs for clock
redundancy. The outputs are configurable and support 1:1, 2:1, 4:1, 1:2 and 1:4
output to input frequency ratios. In addition, a selectable output 180
° phase
control supports advanced clocking schemes with inverted clock signals. The
MPC9315 is specified for the extended temperature range of –40 to +85
°C.
Features
Configurable 8 outputs LVCMOS PLL clock generator
Compatible to various microprocessors such as PowerQUICC I and II
Wide range output clock frequency of 18.75 to 160 MHz
2.5 V and 3.3 V CMOS compatible
Designed for mid-range to high-performance telecom, networking and
computer applications
Fully integrated PLL supports spread spectrum clocking
Supports applications requiring clock redundancy
Max. output skew of 120 ps (80 ps within one bank)
Selectable output configurations (1:1, 2:1, 4:1, 1:2, 1:4 frequency ratios)
Two selectable LVCMOS clock inputs
External PLL feedback path and selectable feedback configuration
Tristable outputs
32-Lead LQFP package
Ambient operating temperature range of -40 to +85
°C
32-Lead Pb-free package available
Functional Description
The MPC9315 utilizes PLL technology to frequency and phase lock its outputs onto an input reference clock. Normal operation
requires a connection of one of the device outputs to the selected feedback (FB0 or FB1) input to close the PLL feedback path.
The reference clock frequency and the output divider for the feedback path determine the VCO frequency. Both must be selected
to match the VCO frequency range. With available output dividers of divide-by-1, divide-by-2 and divide-by-4, the internal VCO
of the MPC9315 is running at either 1x, 2x or 4x of the reference clock frequency. The frequency of the QA, QB, QC output groups
is either the equal, one half or one fourth of the selected VCO frequency and can be configured for each output bank using the
FSELA, FSELB and FSELC pins, respectively. The available output to input frequency ratios are 4:1, 2:1, 1:1, 1:2 and 1:4. The
REF_SEL pin selects one of the two available LVCMOS compatible reference input (CLK0 and CLK1) supporting clock redundant
applications. The selectable feedback input pin allows the user to select different feedback configurations and input to output
frequency ratios. The MPC9315 also provides a static test mode when the PLL supply pin (VCCA) is pulled to logic low state
(GND). In test mode, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The test mode
is intended for system diagnostics, test and debug purposes. This test mode is fully static and the minimum clock frequency spec-
ification does not apply. The outputs can be disabled by deasserting the OE pin (logic high state). In PLL mode, deasserting OE
causes the PLL to lose lock due to no feedback signal presence at FB0 or FB1. Asserting OE will enable the outputs and close
the phase locked loop, also enabling the PLL to recover to normal operation. The MPC9315 is fully 2.5 V and 3.3 V compatible
and requires no external loop filter components. All inputs accept LVCMOS signals while the outputs provide LVCMOS compat-
ible levels with the capability to drive terminated 50
transmission lines. For series terminated transmission lines, each of the
MPC9315 outputs can drive one or two traces giving the devices an effective fanout of 1:18. The device is packaged in a 7x7 mm2
32-lead LQFP package.
The fully integrated PLL of the MPC9315 allows the low skew outputs to lock onto a clock input and distribute it with essentially
zero propagation delay to multiple components on the board. In zero-delay buffer mode, the PLL minimizes phase offset between
the outputs and the reference signal.
MPC9315
LOW VOLTAGE
2.5 V AND 3.3 V PLL
CLOCK GENERATOR
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
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相關代理商/技術參數 |
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|---|---|
| MPC9315FA | 功能描述:鎖相環 - PLL 2.5 3.3V 160MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9315FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC931FA | 制造商:Motorola Inc 功能描述: |
| MPC932 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9330 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3V / 2.5V 1:6 LVCMOS PLL CLOCK GENERATOR |
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