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參數(shù)資料
| 型號： | MPC9350ACR2 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL CLOCK DRIVER LV 32-LQFP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 類型： | PLL 時(shí)鐘發(fā)生器 |
| PLL： | 帶旁路 |
| 輸入： | LVCMOS，晶體 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 200MHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.375 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-LQFP |
| 供應(yīng)商設(shè)備封裝： | 32-TQFP（7x7） |
| 包裝： | 帶卷 (TR) |
DATASHEET
Low Voltage PLL Clock Driver
MPC9350
NRND
MPC9350 REVISION 7 DECEMBER 19, 2012
1
2012 Integrated Device Technology, Inc.
Low Voltage PLL Clock Driver
The MPC9350 is a 2.5 V and 3.3 V compatible, PLL-based clock generator
targeted for high performance clock distribution systems. With output
frequencies of up to 200 MHz and maximum output skews of 150 ps, the
MPC9350 is ideal for the most demanding clock tree designs. The device offers
9 low skew clock outputs, with each one configurable to support the clocking
needs of the various high-performance microprocessors, including the
PowerQUICC II integrated communication microprocessor. The extended
temperature range of the MPC9350 supports telecommunication and networking
requirements. The device employs a fully differential PLL design to minimize
cycle-to-cycle and long-term jitter.
Features
9 Output LVCMOS PLL Clock Generator
25 – 200 MHz Output Frequency Range
2.5 V and 3.3 V Compatible
Compatible to Various Microprocessors Such as PowerQuicc II
Supports Networking,Telecommunications and Computer Applications
Fully Integrated PLL
Configurable Outputs: Divide-by-2, 4 and 8 of VCO Frequency
Selectable Output to Input Frequency Ratio of 8:1, 4:1, 2:1 or 1:1
Oscillator or Crystal Reference Inputs
Internal PLL Feedback
Output Disable
PLL Enable/Disable
Low Skew Characteristics: Maximum 150 ps Output-to-Output
32-Lead LQFP Package, Pb-Free
Temperature Range –40
C to +85C
Functional Description
The MPC9350 generates high frequency clock signals and provides nine exact frequency-multiplied copies of the reference
clock signal. The internal PLL allows the MPC9350 to operate in frequency locked condition and to multiply the input reference
clock. The reference clock frequency and the divider in the internal feedback path determine the VCO frequency. Two selectable
PLL feedback frequency ratios are available on the MPC9350 to provide input frequency range flexibility. The FBSEL pin selects
between divide-by-16 or divide-by-32 of the VCO frequency for PLL feedback. This feedback divider must be selected to match
the VCO frequency range. With the available feedback output dividers, the internal VCO of the MPC9350 is running at either 16x
or 32x of the reference clock frequency. The frequency of the QA, QB, QC and QD outputs is either one half, one fourth or one
eighth of the selected VCO frequency and can be configured for each output bank using the FSELA, FSELB, FSELC and FSELD
pins, respectively. The available output to input frequency ratios are 16:1, 8:1, 4:1 and 2:1. The REF_SEL pin selects the crystal
oscillator input or the LVCMOS compatible reference input (TCLK). TCLK also provides an external test clock in static test mode
when the PLL enable pin (PLL_EN) is pulled to logic low state. In test mode, the selected input reference clock is routed directly
to the output dividers without using the PLL. The test mode is intended for system diagnostics, test and debug purposes. This
test mode is fully static and the minimum clock frequency specification does not apply. The outputs can be disabled by
deasserting the OE pin (logic high state). In PLL mode, deasserting OE maintains PLL lock due to the internal feedback path.
The MPC9350 is fully 2.5 V and 3.3 V compatible and requires no external loop filter components. The on-chip crystal oscillator
requires no external components beyond a series resonant crystal. All inputs except the crystal oscillator interface accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50
transmission
lines. For series terminated transmission lines, each of the MPC9350 outputs can drive one or two traces giving the device an
effective fanout of 1:18. The device is packaged in a 7x7 mm2 32-lead LQFP package.
MPC9350
LOW VOLTAGE
3.3 V AND 2.5 V PLL
CLOCK GENERATOR
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
NRND – Not Recommend for New Designs
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9350D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC9350FA | 功能描述:時(shí)鐘驅(qū)動器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| MPC9350FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
| MPC9351 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Low Voltage PLL Clock Driver |
| MPC9351AC | 功能描述:時(shí)鐘驅(qū)動器及分配 2.5 3.3V 200MHz Clock Generator RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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