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參數(shù)資料
| 型號(hào)： | MPC93R52AC |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 93R SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | LEAD FREE, LQFP-32 |
| 文件頁(yè)數(shù)： | 1/13頁(yè) |
| 文件大小： | 494K |
| 代理商： | MPC93R52AC |
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MPC93R52
Rev. 5, 1/2005
Freescale Semiconductor
Technical Data
Freescale Semiconductor, Inc., 2005. All rights reserved.
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
3.3 V 1:11 LVCMOS Zero Delay
The MPC93R52 is a 3.3 V compatible, 1:11 PLL based clock generator
targeted for high performance clock tree applications. With output frequencies up
to 240 MHz and output skews lower than 200 ps, the device meets the needs of
most demanding clock applications.
Features
Configurable 11 outputs LVCMOS PLL clock generator
Fully integrated PLL
Wide range of output clock frequency of 16.67 MHz to 240 MHz
Multiplication of the input reference clock frequency by 3, 2, 1, 3
÷ 2, 2 ÷ 3,
1
÷ 3, and 1 ÷ 2
3.3 V LVCMOS compatible
Maximum output skew of 200 ps
Supports zero-delay applications
Designed for high-performance telecom, networking and computing
applications
32-lead LQFP package
32-lead Pb-free package available
Ambient Temperature Range – 0°C to +70°C
Pin and function compatible to the MPC952
Functional Description
The MPC93R52 is a fully 3.3 V compatible PLL clock generator and clock driver. The device has the capability to generate
output clock signals of 16.67 to 240 MHz from external clock sources. The internal PLL is optimized for its frequency range and
does not require external look filter components. One output of the MPC93R52 has to be connected to the PLL feedback input
FB_IN to close the external PLL feedback path. The output divider of this output setting determines the PLL frequency multipli-
cation factor. This multiplication factor, F_RANGE and the reference clock frequency must be selected to situate the VCO in its
specified lock range. The frequency of the clock outputs can be configured individually for all three output banks by the FSELx
pins supporting systems with different but phase-aligned clock frequencies.
The PLL of the MPC93R52 minimizes the propagation delay and therefore supports zero-delay applications. All inputs and
outputs are LVCMOS compatible. The outputs are optimized to drive parallel terminated 50
transmission lines. Alternatively,
each output can drive up to two series terminated transmission lines giving the device an effective fanout of 22.
The device also supports output high-impedance disable and a PLL bypass mode for static system test and diagnosis. The
MPC93R52 is package in a 32 ld LQFP.
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
LOW VOLTAGE
3.3 V LVCMOS 1:11
CLOCK GENERATOR
DATA SHEET
MPC93R52
IDT 3.3 V 1:11 LVCMOS Zero Delay Clock Generator
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MPC93R52
1
3.3 V 1:11 LVCMOS Zero Delay
Clock Generator
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC93R52ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 FSL 1-11 LVCMOS PLL Clock Generator, pwr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93R52FA | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 3.3V 240MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC93R52FAR2 | 制造商:Integrated Device Technology Inc 功能描述:Zero Delay PLL Clock Generator Single 32-Pin LQFP T/R 制造商:Integrated Device Technology Inc 功能描述:ZERO DLY PLL CLOCK GEN SGL 32LQFP - Tape and Reel |
| MPC940 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE 1:18 CLOCK DISTRIBUTION CHIP |
| MPC940L | 制造商:Motorola Inc 功能描述: |
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