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參數資料
| 型號： | MPC96877EP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40 |
| 封裝： | 6 X 6 MM, 0.50 MM PITCH, LEAD FREE, MO-220VJJD-2, MLF-40 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 221K |
| 代理商： | MPC96877EP |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
Order number: MPC96877
Rev 0, 04/2004
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice
.
Motorola, Inc. 2004
1.8 V PLL 1:10 Differential SDRAM
Clock Driver
Recommended Applications
DDR II Memory Modules
Zero Delay Board fan-out
Features
1.8-V Phase Lock Loop Clock Driver for (DDR II) Applications
Spread Spectrum Clock Compatible
Operating Frequency: 100 MHz to 340 MHz
1 to 10 differential clock distribution (SSTL_18)
52-Ball VF-BGA (FP-MAPBGA 0.65-mm pitch) and 40-Pin MLF(QFN)
External Feedback Pins (FBIN, FBIN) are used to synchronize the Outputs
to the Input Clocks
Single-Ended Input and Single-Ended Output Modes
Meets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300
Auto Power Down detect logic
Switching Characteristics
Cycle to Cycle Jitter (>165 Mhz): 40ps max.
Output to Output Skew: 40 ps max.
Functional Description
The MPC96877 is a high-performance, low-jitter, low-skew, zero-delay buff-
er that distributes a differential clock input pair (CK, CK) to ten differential pairs
of clock outputs (Yn, Yn) and to one differential pair of feedback clock outputs
(FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK,
CK), the feedback clocks (FBIN, FBIN), the LVCMOS control pins (OE, OS),
and the analog power input (AVDD). When OE is low, the clock outputs, except
FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its
locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously
described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDD is grounded, the PLL is
turned off and bypassed for test purposes. When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An
input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low
power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being dif-
ferential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback
clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within the specified stabilization time.
The MPC96877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from 0
°C to 70°C.
MPC96877
SCALE 2:1
VK SUFFIX
52-BALL FP-MAPBGA PACKAGE
CASE 1544-01
DDR II MEMORY
CLOCK / ZERO DELAY BUFFER
AVAILABLE ORDERING OPTIONS
TA
52-Ball BGA
40-Pin QFN
0
°C to 70°C
MPC96877VK
(Pb-Free)
MPC96877EP
(Pb-Free)
EP SUFFIX
40-PIN MLF/QFN PACKAGE
CASE 1545-01
SCALE 2:1
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相關代理商/技術參數 |
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| MPC96877VK | 功能描述:時鐘發生器及支持產品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC96877VKR2 | 功能描述:時鐘發生器及支持產品 DDR2 PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC970 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:LOW VOLTAGE PLL CLOCK DRIVER |
| MPC972 | 制造商:Motorola Inc 功能描述: |
| MPC972FA | 制造商:Freescale Semiconductor 功能描述: |
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