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參數資料
| 型號： | MPC99J93FAR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| 封裝： | PLASTIC, LQFP-32 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 213K |
| 代理商： | MPC99J93FAR2 |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC99J93/D
Rev 1, 08/2003
MOTOROLA TIMING SOLUTIONS
1
Product Preview
Intelligent Dynamic Clock
Switch (IDCS) PLL Clock
Driver
The MPC99J93 is a PLL clock driver designed specifically for redun-
dant clock tree designs. The device receives two differential LVPECL
clock signals from which it generates 5 new differential LVPECL clock
outputs. Two of the output pairs regenerate the input signals frequency
and phase while the other three pairs generate 2x, phase aligned clock
outputs.
Features:
Fully Integrated PLL
Intelligent Dynamic Clock Switch
LVPECL Clock Outputs
LVCMOS Control I/O
3.3V Operation
32--Lead LQFP Packaging
Functional Description
The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection
of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary
clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase
disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).
Figure 1. Block Diagram
CLK0
CLK1
Ext_FB
Sel_Clk
Dynamic Switch
Logic
PLL
PLL_En
÷2
÷4
Qb0
Qb1
Qb2
Qa0
Qa1
MR
Man_Override
Clk_Selected
Inp1bad
Inp0bad
Alarm_Reset
OR
200 -- 360 MHz
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E
Motorola Inc. 2003
MPC99J93
FA SUFFIX
32--LEAD LQFP PACKAGE
CASE 873A
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