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參數(shù)資料
| 型號(hào)： | MS6323ASU |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 16-Bits Stereo Audio DAC |
| 中文描述： | 16位立體聲音頻DAC |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 281K |
| 代理商： | MS6323ASU |
MO
SA
MS6323
16-Bits Stereo Audio DAC
REV1
5
www.mosanalog.com.tw
TIMING AND DATA FORMAT
The MS6323 accepts input serial data formats of 16-bit word length. Left and right data words are time
multiplexed. The MSB must always be first. The format of data input is shown in Figs. 2 and 3. With a HIGH level on
the word select input (WS), data is placed in the left input register and with LOW level on the WS input, data is placed
in the right register (Fig. 1). The data in the input registers are simultaneously latched in the output registers which
control the bit switches. Internal bias currents I
BL
and I
BR
are each added to the full scale output current I
FS
in order to
achieve the maximum dynamic range at the outputs of OP1 and OP2(Fig. 1). In this way the maximum dynamic range
is achieved over the entire power supply range.
RIGHT
WS
BCK
DATA
LSB
MSB
t
r
t
HB
t
f
t
cr
t
LB
t
HW
t
SW
LEFT
t
SD
t
HD
Fig.2 Timing and input signals.
0
1
2
15
14
13
2
1
0
MSB
LSB
15
14
13
2
1
0
MSB
LSB
RIGHT
LEFT
WS
BCK
DATA
Fig.3 Format of input signals.
Data format (BCK, WS, DATA)
Symbol
V
IL
Input LOW level
V
IH
Input HIGH level
l
I
IL
l
Input Leakage Current LOW
l
I
IH
l
Input Leakage Current HIGH
f
BCK
Input Clock Frequency
BR
Bit Rate Data Input
f
WS
Word Select Input
t
r
Rise Time
t
f
Fall Time
t
C
r
Bit Clock Cycle Time
t
HB
Bit Clock High Time
t
LB
Bit Clock Low Time
t
SD
Data Set-up Time
t
HD
Data Hold Time to Bit Clock
t
HW
Word Select Hold Time
t
SW
Word Select Set-up Time
Parameter
Conditions
Min
-
0.7V
DD
-
-
-
-
-
-
-
54
15
15
12
2
2
12
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Max
0.3V
DD
-
10
10
18.4
18.4
384
12
12
-
-
-
-
-
-
-
Unit
V
V
μ
A
μ
A
MHz
Mbits/s
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
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