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參數資料
| 型號： | MT46V64M8TG-75 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數據速率的DDR SDRAM內存 |
| 文件頁數： | 1/68頁 |
| 文件大小： | 2555K |
| 代理商： | MT46V64M8TG-75 |
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1
512Mb: x4, x8, x16 DDR SDRAM
512Mx4x8x16DDR_B.p65 – Rev. B; Pub 4/01
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2001, Micron Technology, Inc.
512Mb: x4, x8, x16
DDR SDRAM
ADVANCE
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
DOUBLE DATA RATE
(DDR) SDRAM
MT46V128M4 –32 Meg x 4 x 4 banks
MT46V64M8 – 16 Meg x 8 x4 banks
MT46V32M16 – 8 Meg x16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
www.micron.com/datasheetsPIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
FEATURES
V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data (x16 has
two – one per byte)
Programmable burst lengths: 2, 4, or 8
x16 has programmable IOL/IOV.
Concurrent auto precharge option is supported
Auto Refresh and Self Refresh Modes
Longer lead TSOP for improved reliability (OCPL)
2.5V I/O (SSTL_2 compatible)
OPTIONS
Configuration
128 Meg x 4
(32 Meg x 4 x 4 banks)
64 Meg x 8
(16 Meg x 8 x 4 banks)
32 Meg x 16
(8 Meg x 16 x 4 banks)
Plastic Package – OCPL
66-pin TSOP (standard 22.3mm length)
(400 mil width, 0.65mm pin pitch)
Timing – Cycle Time
7.5ns @ CL = 2 (DDR266B)
1
7.5ns @ CL = 2.5 (DDR266B)
2
10ns @ CL = 2 (DDR200)
2
Self Refresh
Standard
Low Power
MARKING
128M4
64M8
32M16
TG
-75Z
-75
-8
none
L
NOTE:
1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
128 Meg x 4
32 Meg x 4 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
4K (A0–A9, A11, A12)
64 Meg x 8
16 Meg x 8 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
2K (A0–A9, A11)
32 Meg x 16
8 Meg x 16 x 4 banks
8K
8K (A0–A12)
4 (BA0, BA1)
1K (A0–A9)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
DNU
V
REF
V
SS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
VssQ
DQ7
NC
V
DD
Q
LDQS
NC
V
DD
DNU
LDM
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
x16
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x8
x4
V
SS
NC
V
SS
Q
NC
DQ3
V
DD
Q
NC
NC
V
SS
Q
NC
DQ2
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
NC
V
DD
Q
NC
NC
V
DD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
x8
x4
V
DD
NC
V
DD
Q
NC
DQ0
V
SS
Q
NC
NC
V
DD
Q
NC
DQ1
V
SS
Q
NC
NC
V
DD
Q
NC
NC
V
DD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
KEY TIMING PARAMETERS
SPEED
GRADE
-75
-75
-8
CLOCK RATE
CL = 2**
133 MHz
100 MHz
100 MHz
DATA-OUT
WINDOW* WINDOW
2.5ns
2.5ns
3.4ns
ACCESS
DQS-DQ
SKEW
+0.5ns
+0.5ns
+0.6ns
CL = 2.5**
133 MHz
133 MHz
125 MHz
±0.75ns
±0.75ns
±0.8ns
*Minimum clock rate @ CL = 2 (-8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
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