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參數資料
| 型號： | MT48LC8M16A2 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數： | 1/4頁 |
| 文件大小： | 115K |
| 代理商： | MT48LC8M16A2 |
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
x16 Addendum
MT48lc8m16a2_addendum.fm - Rev. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
2002, Micron Technology Inc.
128Mb x16
SDRAM Addendum
PRELIMINARY
SYNCHRONOUS
DRAM
MT48LC8M16A2 – 2 MEG X 16 X 4 BANKS
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
FEATURES
Supports PC100 and PC133 functionality
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
Self Refresh Mode; standard and low power
LVTTL-compatible inputs and outputs
Single +3.3V ±0.3V power supply
64ms, 4,096-cycle refresh
Part Number:
MT48LC8M16A2TG-6A
ADDENDUM CHANGES
The standard 128Mb SDRAM data sheets also per-
tain to the x16 device and should be referenced for a
complete description of SDRAM functionality and
operating modes. However, to meet the faster speed
grades, some of the AC timing parameters are slightly
different. This addendum data sheet will concentrate
on the key differences required to support the
enhanced speeds.
The Micron 128Mb data sheet provides full specifi-
cations and functionality unless specified herein.
OPTION
Configuration
8 Meg x 16 (2 Meg x 16 x 4 banks)
WRITE Recovery (
t
WR)
t
WR = “2 CLK”
1
Package
Plastic Package – OCPL
2
54-pin TSOP II (400 mil)
Timing (Cycle Time)
6.0ns @ CL = 3
Self Refresh
Standard
Operating Temperature Range
Commercial (0
o
C to +70
o
C)
MARKING
8M16
A2
NOTE:
1. Refer to Micron Technical Note: TN-48-05.
2. Off-center parting line.
TG
-6A
None
None
8 MEG X 16
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
2 Meg x 16 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
512 (A0–A8)
KEY TIMING PARAMETERS
SPEED
GRADE
CLOCK
FREQUENCY
ACCESS
TIME
CL = 3*
SETUP
TIME
HOLD
TIME
-6A
167 MHz
5.4ns
1.5ns
0.8ns
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相關代理商/技術參數 |
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