
Products and specifications discussed herein are subject to change by Micron without notice.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM II
Features
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
288Mb_RLDRAM_II_CIO_D1.fm - Rev N 5/08 EN
1
2003 Micron Technology, Inc. All rights reserved.
CIO RLDRAM II
MT49H32M9 – 32 Meg x 9 x 8 Banks
MT49H16M18 – 16 Meg x 18 x 8 Banks
MT49H8M36 – 8 Meg x 36 x 8 Banks
Features
400 MHz DDR operation (800 Mb/s/pin data rate)
28.8 Gb/s peak bandwidth (x36 at 400 MHz
clock frequency)
Organization
– 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36
8 internal banks for concurrent operation and
maximum bandwidth
Reduced cycle time (20ns at 400 MHz)
Nonmultiplexed addresses (address multiplexing
option available)
SRAM-type interface
Programmable READ latency (RL), row cycle time,
and burst sequence length
Balanced READ and WRITE latencies in order to
optimize data bus utilization
Data mask for WRITE commands
Differential input clocks (CK, CK#)
Differential input data clocks (DKx, DKx#)
On-die DLL generates CK edge-aligned data and
output data clock signals
Data valid signal (QVLD)
32ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32ms)
144-ball BGA package
HSTL I/O (1.5V or 1.8V nominal)
25–60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
On-die termination (ODT) RTT
Figure 1:
144-Ball BGA
Notes: 1. Contact Micron for availability of industrial
temperature products.
2. Contact Micron for availability of Pb-free
products.
3. The FBGA package is being phased out.
Options
Marking
Clock cycle timing
– 2.5ns (400 MHz)
-25
– 3.3ns (300 MHz)
-33
– 5ns (200 MHz)
-5
Configuration
– 32 Meg x 9
32M9
– 16 Meg x 18
16M18
– 8 Meg x 36
8M36
Operating temperature
– Commercial (0° to +95°C)
None
– Industrial (TC = –40°C to +95°C;
TA = –40°C to +85°C)
IT1
Package
– 144-ball BGA
FM1
– 144-ball BGA (Pb-free)
BM2
– 144-ball FBGA
HU3
– 144-ball FBGA (Pb-free)
HT2, 3