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參數(shù)資料
| 型號(hào)： | MT4LC4M4E9DJS |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 MEG x 4 EDO DRAM |
| 中文描述： | 4邁可× 4 EDO公司的DRAM |
| 文件頁(yè)數(shù)： | 1/20頁(yè) |
| 文件大小： | 360K |
| 代理商： | MT4LC4M4E9DJS |
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1
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4 MEG x 4
FPM DRAM
4 MEG x 4 FPM DRAM PART NUMBERS
REFRESH
PART NUMBER
MT4LC4M4B1DJ-6
MT4LC4M4B1DJ-6 S 3.3V
MT4LC4M4B1TG-6
MT4LC4M4B1TG-6 S 3.3V
MT4LC4M4A1DJ-6
MT4LC4M4A1DJ-6 S 3.3V
MT4LC4M4A1TG-6
MT4C4M4A1TG-6 S
MT4C4M4B1DJ-6
MT4C4M4B1DJ-6 S
MT4C4M4B1TG-6
MT4C4M4B1TG-6 S
MT4C4M4A1DJ-6
MT4C4M4A1DJ-6 S
MT4C4M4A1TG-6
MT4C4M4A1TG-6 S
V
CC
ADDRESSING PACKAGE REFRESH
3.3V
2K
2K
3.3V
2K
2K
3.3V
4K
4K
3.3V
4K
3.3V
4K
5V
2K
5V
2K
5V
2K
5V
2K
5V
4K
5V
4K
5V
4K
5V
4K
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
Standard
Self
MT4LC4M4B1, MT4C4M4B1
MT4LC4M4A1, MT4C4M4A1
site: www.micronsemi.com/mti/msp/html/datasheet.html
DRAM
FEATURES
Industry-standard x4 pinout, timing, functions,
and packages
High-performance, low-power CMOS silicon-gate
process
Single power supply (+3.3V ±0.3V or +5V ±0.5V)
All inputs, outputs and clocks are TTL-compatible
Refresh modes: RAS#-ONLY, HIDDEN and CAS#-
BEFORE-RAS# (CBR)
Optional self refresh (S) for low-power data
retention
11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)
FAST-PAGE-MODE (FPM) access
5V tolerant inputs and I/Os on 3.3V devices
OPTIONS
Voltage
3.3V
5V
Refresh Addressing
2,048 (2K) rows
4,096 (4K) rows
Packages
Plastic SOJ (300 mil)
Plastic TSOP (300 mil)
Timing
50ns access
60ns access
Refresh Rates
Standard Refresh
Self Refresh (128ms period)
NOTE:
1. The 4 Meg x 4 FPM DRAM base number differenti-
ates the offerings in one place—MT4LC4M4B1. The
fifth field distinguishes various options: B1
designates a 2K refresh and A1 designates a 4K
refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
MARKING
LC
C
B1
A1
DJ
TG
-5
-6
None
S*
Part Number Example:
MT4LC4M4B1DJ
**NC on 2K refresh and A11 on 4K refresh options.
PIN ASSIGNMENT (Top View )
V
CC
DQ0
DQ1
WE#
RAS#
**NC/
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ3
DQ2
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
WE#
RAS#
**NC/
A11
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
8
9
10
11
12
13
26
25
24
23
22
21
19
18
17
16
15
14
V
SS
DQ3
DQ2
CAS#
OE#
A9
A8
A7
A6
A5
A4
V
SS
24/26-Pin SOJ
24/26-Pin TSOP
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
84ns
110ns
t
RAC
50ns
60ns
t
PC
20ns
35ns
t
AA
25ns
30ns
t
CAC
13ns
15ns
t
RP
30ns
40ns
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| MT4C4M4E9DJS | 4 MEG x 4 EDO DRAM |
| MT4LC4M4E9TGS | 4 MEG x 4 EDO DRAM |
| MT4C4M4E9TGS | 4 MEG x 4 EDO DRAM |
| MT4LDT832HG-5XS | SMALL-OUTLINE DRAM MODULE |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT4LC4M4E9TG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:4 MEG x 4 EDO DRAM |
| MT4LC4M4E9TGS | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:4 MEG x 4 EDO DRAM |
| MT4LC8M8B6DJ-5 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
| MT4LC8M8B6DJ-5S | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
| MT4LC8M8B6DJ-6 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DRAM |
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