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參數資料
| 型號： | MT4LC8M8P4TG-6 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DRAM |
| 中文描述： | 內存 |
| 文件頁數： | 1/20頁 |
| 文件大小： | 382K |
| 代理商： | MT4LC8M8P4TG-6 |
1
8 Meg x 8 FPM DRAM
D19_2.p65 – Rev. 5/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
8 MEG x 8
FPM DRAM
FEATURES
Single +3.3V ±0.3V power supply
Industry-standard x8 pinout, timing, functions,
and packages
13 row, 10 column addresses (E1) or
12 row, 11 column addresses (B6)
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are LVTTL-
compatible
FAST PAGE MODE (FPM) access
4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
Optional self refresh (S) for low-power data
retention
OPTIONS
Refresh Addressing
4,096 (4K) rows
8,192 (8K) rows
MARKING
B6
E1
Plastic Packages
32-pin SOJ (400 mil)
32-pin TSOP (400 mil)
DJ
TG
Timing
50ns access
60ns access
-5
-6
Refresh Rates
Standard Refresh (64ms period)
Self Refresh (128ms period)
NOTE:
1. The 8 Meg x 8 FPM DRAM base number
differentiates the offerings in one place—
MT4LC8M8E1. The fifth field distinguishes
various options: E1 designates an 8K refresh and
B6 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
None
S*
Part Number Example:
MT4LC8M8E1DJ-5
DRAM
MT4LC8M8E1, MT4LC8M8B6
site: www.micron.com/products/datasheets/dramds.html
8 MEG x 8 FPM DRAM PART NUMBERS
REFRESH
ADDRESSING
8K
8K
8K
8K
4K
4K
4K
4K
PART NUMBER
MT4LC8M8E1DJ-x
MT4LC8M8E1DJ-x S
MT4LC8M8E1TG-x
MT4LC8M8E1TG-x S
MT4LC8M8B6DJ-x
MT4LC8M8B6DJ-x S
MT4LC8M8B6TG-x
MT4LC8M8B6TG-x S
PACKAGE
SOJ
SOJ
TSOP
TSOP
SOJ
SOJ
TSOP
TSOP
REFRESH
Standard
Self
Standard
Self
Standard
Self
Standard
Self
x = speed
**A12 on E1 version, NC on B6 version
32-Pin TSOP
V
CC
DQ0
DQ1
DQ2
DQ3
NC
V
CC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
V
SS
CAS#
OE#
NC/
A12
**
A11
A10
A9
A8
A7
A6
V
SS
32-Pin SOJ
V
CC
DQ0
DQ1
DQ2
DQ3
NC
V
CC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
SS
DQ7
DQ6
DQ5
DQ4
Vss
CAS#
OE#
NC
/
A12
**
A11
A10
A9
A8
A7
A6
V
SS
PIN ASSIGNMENT (Top View )
KEY TIMING PARAMETERS
SPEED
-5
-6
t
RC
90ns
110ns
t
RAC
50ns
60ns
t
PC
30ns
35ns
t
AA
25ns
30ns
t
CAC
13ns
15ns
GENERAL DESCRIPTION
The 8 Meg x 8 DRAMs are high-speed CMOS, dy-
namic random-access memory devices containing
67,108,864 bits organized in a x8 configuration. The
8 Meg x 8 DRAMs are functionally organized as 8,388,608
locations containing eight bits each. The 8,388,608
memory locations are arranged in 8,192 rows by 1,024
columns for the MT4LC8M8E1 or 4,096 rows by 2,048
columns for the MT4LC8M8B6. During READ or WRITE
cycles, each location is uniquely addressed via the
address bits. First, the row address is latched by the
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