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參數(shù)資料
| 型號(hào)： | MT55L64L32F1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 64K x 32,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
| 中文描述： | 64K的x 32,3.3六/ O的ZBT SRAM的（處理器，3.3V的輸入/輸出，靜態(tài)內(nèi)存） |
| 文件頁(yè)數(shù)： | 1/23頁(yè) |
| 文件大小： | 406K |
| 代理商： | MT55L64L32F1 |
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2Mb: 128K x 18, 64K x 32/36 3.3V I/O, Flow-Through ZBT SRAM
MT55L128L18F1_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
2Mb: 128K x 18, 64K x 32/36
3.3V I/O, FLOW-THROUGH ZBT SRAM
2Mb
ZBT
SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 10ns and 12ns
Single +3.3V ±5% power supply
Advanced control logic for minimum control
signal interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs eliminate
the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
100-pin TQFP package
165-pin FBGA package
Pin/function compatibility with 4Mb, 8Mb, and
16Mb ZBT SRAM
Automatic power-down
OPTIONS
Timing (Access/Cycle/MHz)
7.5ns/10ns/100 MHz
9ns/12ns/83 MHz
MARKING*
-10
-12
Configurations
128K x 18
64K x 32
64K x 36
MT55L128L18F1
MT55L64L32F1
MT55L64L36F1
Package
100-pin TQFP
165-pin FBGA
T
F
Temperature
Commercial (0°C to +70°C)
None
Part Number Example:
MT55L128L18F1T-10
* A Part Marking Guide for the FBGA devices can be found on Micron’s
http://www.micron.com/support/index.html.
MT55L128L18F1,
MT55L64L32F1, MT55L64L36F1
3.3V V
DD
, 3.3V I/O
GENERAL DESCRIPTION
The Micron
Zero Bus Turnaround
(ZBT
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
The MT55L128L18F1 and MT55L64L32/36F1 SRAMs
integrate a 128K x 18, 64K x 32, or 64K x 36 SRAM core
with advanced synchronous peripheral circuitry and a
2-bit burst counter. These SRAMs are optimized for 100
percent bus utilization, eliminating turnaround cycles
for READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
**JEDEC-standard MS-026 BHA (LQFP).
100-Pin TQFP**
165-Pin FBGA
(Preliminary Package Data)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55L64L36F1 | 64K x 36,3.3V I/O, ZBT SRAM(2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
| MT55L64L36P1 | 64K x 36, 3.3V I/O, ZBT SRAM( 2Mb,3.3V輸入/輸出，靜態(tài)RAM) |
| MT58L128L18FT-10 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L18FT-6.8 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L18FT-7.5 | 2Mb: 128K x 18, 64K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L64L32F1T-10 | 制造商:Cypress Semiconductor 功能描述:64KX32 SRAM PLASTIC TQFP 3.3V |
| MT55L64L32F1T-12 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 2M-Bit 64K x 32 9ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L64L32F1T-12IT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55L64L32P1T10 | 制造商:MT 功能描述:New |
| MT55L64L36F1T-12 | 制造商:Cypress Semiconductor 功能描述:64KX36 SRAM PLASTIC TQFP 3.3V |
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