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參數資料
| 型號： | MT58L512Y32D |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16Mb SYNCBURST⑩ SRAM |
| 中文描述： | ⑩的SRAM 16Mb的SYNCBURST |
| 文件頁數： | 1/34頁 |
| 文件大小： | 526K |
| 代理商： | MT58L512Y32D |
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16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
16Mb SYNCBURST
SRAM
FEATURES
Fast clock and OE# access times
Single +3.3V ±0.165Vor 2.5V ±0.125V power supply
(V
DD
)
Separate +3.3V or 2.5V isolated output buffer
supply (V
DD
Q)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL
WRITE
Three chip enables for simple depth expansion and
address pipelining
Clock-controlled and registered addresses, data I/Os
and control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down
100-pin TQFP package
165-pin FBGA package
Low capacitive bus loading
x18, x32, and x36 versions available
OPTIONS
Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
TQFP MARKING*
-6
-7.5
-10
Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V V
DD
, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
MT58L1MY18D
MT58L512Y32D
MT58L512Y36D
MT58V1MV18D
MT58V512V32D
MT58V512V36D
Packages
100-pin TQFP (3-chip enable)
165-pin FBGA
T
F
Operating Temperature Range
Commercial (0oC to +70oC)
None
*See page 34 for FBGA package marking guide.
Part Number Example:
MT58L1MY18DT-7.5
MT58L1MY18D, MT58V1MV18D,
MT58L512Y32D, MT58V512V32D,
MT58L512Y36D, MT58V512V36D
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
, 2.5V
I/O, Pipelined, Double-Cycle Deselect
GENERAL DESCRIPTION
The Micron
SyncBurst
SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process.
Micron’s 16Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all addresses,
all data inputs, active LOW chip enable (CE#), two
additional chip enables for easy depth expansion (CE2,
CE2#), burst control inputs (ADSC#, ADSP#, ADV#),
byte write enables (BWx#) and global write (GW#). Note
that CE2# is not available on the T Version.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
100-Pin TQFP
1
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
165-Pin FBGA
(Preliminary Package Data)
相關PDF資料 |
PDF描述 |
|---|---|
| MT58L64L18F | 64K x 18, 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態RAM) |
| MT58L32L32F | 32K x 32， 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出,流通式同步脈沖靜態RAM) |
| MT58L32L36F | 32K x 36， 3.3V I/O, Flow-Through SyncBurst SRAM(1Mb,3.3V輸入/輸出，流通式同步脈沖靜態RAM) |
| MT58L64L18P | 64K x 18, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環取消選擇，同步脈沖靜態存儲器) |
| MT58L32L32P | 32K x 32, 3.3V I/O, Pipelined, SCD SyncBurst SRAM(1Mb,3.3V輸入/輸出，流水線式，單循環取消選擇，同步脈沖靜態存儲器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MT58L512Y32DT-10 | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y32DT-10 ES | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V |
| MT58L512Y32DT-6 | 制造商:Cypress Semiconductor 功能描述:DS2KX32 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L512Y32PT-10 IT | 制造商:Cypress Semiconductor 功能描述:16MB 512KX32 SRAM PLASTIC IND |
| MT58L512Y32PT-6 | 制造商:Cypress Semiconductor 功能描述:512KX32 SRAM PLASTIC TQFP 3.3V |
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