- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄380523 > MT5C1001 (Electronic Theatre Controls, Inc.) SRAM PDF資料下載
參數(shù)資料
| 型號： | MT5C1001 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SRAM |
| 中文描述： | 靜態(tài)存儲器 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大小： | 166K |
| 代理商： | MT5C1001 |
SRAM
MT5C1001
Limited Availability
Austin Semiconductor, Inc.
MT5C1001
Rev. 2.0 2/00
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
High Speed: 20, 25, 35, and 45
Battery Backup: 2V data retention
Low power standby
Single +5V (+10%) Power Supply
Easy memory expansion with CE\ and OE\ options.
All inputs and outputs are TTL compatible
Three-state output
OPTIONS
Timing
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
MARKING
-20
-25
-35
-45
-55*
-70*
Package(s)
Ceramic DIP (400 mil)
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
C
EC
F
DCJ
No. 109
No. 207
No. 303
No. 501
Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
Military (-55
o
C to +125
o
C)
IT
XT
2V data retention/low power
L
*Electrical characteristics identical to those provided for the
45ns access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-92316
MIL-STD-883
28-Pin DIP (C)
(400 MIL)
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
32-Pin Flat Pack (F)
GENERAL DESCRIPTION
The MT5C1001 employs low power, high-performance
silicon-gate CMOS technology. Static design eliminates the
need for external clocks or timing strobes while CMOS circuitry
reduces power consumption and provides for greater
reliability.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE|) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
The “L” version provides an approximate 50 percent
reduction in CMOS standby current (I
SBC2
) over the standard
version.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
1M x 1 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.austinsemiconductor.com
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
A11
A12
A13
A14
A15
NC
A16
A17
A18
A19
Q
WE\
Vss
Vcc
A9
A8
A7
A6
A5
A4
NC
A3
A2
A1
A0
D
CE\
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
A10
A11
A12
NC
A13
A14
A15
NC
A16
A17
A18
A19
NC
Q
WE\
Vss
Vcc
NC
A9
A8
A7
A6
A5
A4
A3
NC
A2
NC
A1
A0
D
CE\
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT5C1001C | SRAM |
| MT5C1001C-20L | SRAM |
| MT5C1001C-IT | SRAM |
| MT5C1001DCJ | SRAM |
| MT5C1001DCJ-70 | SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT5C1001_05 | 制造商:AUSTIN 制造商全稱:Austin Semiconductor 功能描述:1M x 1 SRAM SRAM MEMORY ARRAY |
| MT5C1001-45 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| MT5C1001-45AT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| MT5C1001-45IT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
| MT5C1001-45L | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x1 SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復。