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參數(shù)資料
| 型號： | MT8952BPR |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 2.5M bps, SERIAL COMM CONTROLLER, PQCC28 |
| 封裝： | PLASTIC, MS-018AB, LCC-28 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大小： | 602K |
| 代理商： | MT8952BPR |
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Formats data as per X.25 (CCITT) level-2
standards
Go-Ahead sequence generation and detection
Single byte address recognition
Microprocessor port and directly accessible
registers for flexible operation and control
19 byte FIFO in both send and receive paths
Handshake signals for multiplexing data links
High speed serially clocked output (2.5 Mbps)
ST-BUS compatibility with programmable channel
selection for data and separate timeslot for
control information
Independent watchdog timer
Facility to disable protocol functions
Low power ISO-CMOS technology
Applications
Data link controllers and protocol generators
Digital sets, PBXs and private packet networks
D-channel controller for ISDN basic access
C-channel controller to Digital Network Interface
Circuits (typically MT8972)
Interprocessor communication
Description
The MT8952B HDLC Protocol Controller frames and
formats data packets according to X.25 (Level 2)
Recommendations from the CCITT.
November 2005
Ordering Information
MT8952BE
28 Pin PDIP
Tubes
MT8952BP
28 Pin PLCC
Tubes
MT8952BS
28 Pin SOIC
Tubes
MT8952BPR
28 Pin PLCC
Tape & Reel
MT8952BE1
28 Pin PDIP*
Tubes
MT8952BP1
28 Pin PLCC*
Tubes
MT8952BPR1 28 Pin PLCC*
Tape & Reel
MT8952BS1
28 Pin SOIC*
Tubes
*Pb Free Matte Tin
-40
°C to +85°C
ISO-CMOS ST-BUSTM Family
MT8952B
HDLC Protocol Controller
Data Sheet
Figure 1 - Functional Block Diagram
D0-D7
A0-A3
R/W
CS
E
IRQ
WD
VDD
VSS
RST
TEOP
CDSTo
F0i
CKi
RxCEN
TxCEN
CDSTi
REOP
C-Channel
Interface
Micro
Processor
Interface
Receive
FIFO
Transmit
FIFO
Transmit
Logic
Zero
Insertion
Flag/Abort
Generator
Address
Decoder
Interrupt
Registers
Control
and Status
Register
Timing
Logic
Receive Logic
Address
Detection
Zero
Deletion
Flag/Abort/
Idle
Detection
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT8952BPR1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC CONTROLLER, PLCC - Tape and Reel |
| MT8952BS | 制造商:Microsemi Corporation 功能描述: |
| MT8952BS1 | 制造商:Microsemi Corporation 功能描述:PB FREE HDLC PROTOCOL CONTROLLER - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE HDLC PROTOCOL CONTROLLER |
| MT8960 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Integrated PCM Filter Codec |
| MT8960AE | 制造商:ZARLINK 功能描述: |
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