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參數資料
| 型號： | MT90733AP |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網絡 |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數： | 1/8頁 |
| 文件大小： | 52K |
| 代理商： | MT90733AP |
5-23
MT90733
DS3 Framer (DS3F)
Advance Information
Features
DS3 payload access in either bit-serial or
nibble-parallel mode
C-bit parity or M13 operating mode
Separate interface for C-bits
Detect and generate DS3 AIS, and idle signals
Transmit reference generator for serial
operation
Transmit and receive FEAC channel under
software control
Transmit single errors: framing, FEBE, C-bit
parity, and P-bit parity
FEBE, C-bit and P-bit performance counters
Transmit-to-Receive and Receive-to-Transmit
loopbacks
Applications
Subrate multiplexing
Wideband data or video transport
DS3 monitor and test
Channel extenders
Description
The MT90733 DS3 Framer (DS3F) is designed for
mapping broadband payloads into the DS3 frame for-
mat, which meets ANSI’s T1.107-1988 and supple-
ment T1.107a-1990.
Although the C-bit parity format is recommended, the
DS3F can also operate in the M13 mode. In the C-bit
parity format, the DS3F provides a separate interface
for selected C-bits. The DS3F also provides software
access for transmitting and receiving the FEAC chan-
nel, and generates and detects DS3 AIS, DS3 idle, P-
bit parity and C-bit parity. In addition, performance
counters are provided, as well as the ability to gener-
ate single framing, FEBE, C-bit parity and P-bit parity
errors. The payload interface is selectable through
software as either a bit-serial or nibble-parallel format.
Figure 1 - Functional Block Diagram
CRDCC
STUFC
STUFD
CRF
CRCK
CRD
X1
X2
D3RD
D3RC
FORCFEBE
FORCEPP
FORCECP
D3TD
D3TC
CXDCC
CXF
CXCK
CXD
OENA
FORCEOE
Output
μ
P I/O
Transmit
Frame
Reference
Generator
N.C.
N.C.
N.C.
RDS
RCS
RCG
RFS
RNIB3
RNIB2
RNIB1
RNIB0
RCN
N.C.
RFN
SEL
RD
ALE
WR
AD(7-0)
Terminal Side
Serial
Parallel
Line Side
N.C.
N.C.
XCK
XFSI
XDS
N.C.
N.C.
N.C.
XFNO
XCN
XCK
N.C.
XNIB3
XNIB2
XNIB1
XNIB0
Input
FE
DS3
Send
DS3
Interpreter
DS3
Receive
TDOUT
TCG
TFOUT
TCOUT
TFIN
TCIN
Receive
Transmit
ISSUE 1
May 1995
CMOS
Ordering Information
MT90733AP
68 Pin PLCC
-40° to 85°C
U.S. Patent Number 5040170
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