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參數(shù)資料
| 型號(hào)： | MT9085B |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | PAC - Parallel Access Circuit(并行存取電路) |
| 中文描述： | 委員會(huì)-并行訪問(wèn)電路（并行存取電路） |
| 文件頁(yè)數(shù)： | 1/21頁(yè) |
| 文件大小： | 111K |
| 代理商： | MT9085B |
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2-125
Features
Configurable for parallel-to-serial or
serial-to-parallel conversion of 1024 channels
Supports serial data rates of 2.048 Mbit/s or
4.096 Mbit/s
Interfaces to Mitel’s MT9080 Switch Matrix
Module (SMX)
Generates all framing signals required in 1K or
2K switching applications
Expandable to 2048ch. systems
Compatible to ST-BUS
Applications
Custom designed small and medium digital
switch matrices using Mitel MT9080B
Rate conversion applications
Interfacing a parallel system bus to devices
utilizing serial I/O
Telephony:PBX, CO, digital cross connects,
digital local loop
Datacom: Integrated Access Concentrators,
WAN/LAN gateways
Description
The MT9085 Parallel Access Circuit (PAC) provides
an interface between an 8 bit, parallel time division
multiplexed bus and a serial time division multiplexed
bus. A single PAC device will accept data clocked out
on the parallel bus of the Mitel MT9080 (SMX) and
output it on 32/16 time division multiplexed serial bus
streams. A second device can be configured to
perform the conversion from the serial format into an
SMX compatible parallel format. The time division,
serial multiplexed streams may operate at 2.048
Mbit/s or at 4.096 Mbit/s. The PAC generates all
framing signals required by the SMX for 1024 and
2048 channel configurations.
Figure 1 - Functional Block Diagram
S0
S1
S30
S31
LOAD
C16
C4
Parallel/Serial
VSS
VDD
C16
C4
Shift
Registers
Address
Decoder
Timing
Generation
Mode
Control
P0
P7
C4i
F0i
C16i
C2o
C4o
F0o
DFPo
DFPo
CFPo
OE
MCA
MCB
CKD
2/4S
Ordering Information
MT9085BP
68 Pin PLCC
-40
°
C to 70
°
C
DS5141
ISSUE 4
March 1999
MT9085B
PAC - Parallel Access Circuit
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