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參數(shù)資料
| 型號(hào)： | MTV030 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | On-Screen Display with Auto-Sizing Controller |
| 中文描述： | 屏幕顯示與自動(dòng)上漿控制器 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 372K |
| 代理商： | MTV030 |
7/21
MTV030 Revision 1.0 10/15/1999
MTV030
MYSON
TECHNOLOGY
3.4 Horizontal display control
The horizontal display control is used to generate control timing for horizontal display based on double char-
acter width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and
HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display char-
acters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calcu-
lated with the following equation,
Horizontal delay time = ( HORD * 6 + 49) * P - phase error detection pulse width
Where P = One pixel display time = One horizontal line display time / (HORR*12)
3.5 Phase lock loop (PLL)
On-chip PLL generates system clock timing (VCLK) by tracking the input HFLB and horizontal resolution reg-
ister (HORR). The frequency of VCLK is determined by the following equation:
VCLK Freq = HFLB Freq * HORR * 12
The VCLK frequency ranges from 6MHz to 150MHz selected by (VCO1, VCO0). In addition, when HFLB input
is not present to MTV030, the PLL will generate a specific system clock, approximately 2.5MHz, by a built-in
oscillator to ensure data integrity.
3.6 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which
are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4 and Figure 5. Each dis-
play register has its corresponding character address on ADDRESS byte, its corresponding background color,
1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at col-
umn 30 for row 0 to row 14 of attribute bytes, it is used to set character size to each respective row. If double
width character is chosen, only even column characters could be displayed on screen and the odd column
characters will be hidden.
FIGURE 4. Address Bytes of Display Registers Memory Map
ROW #
COLUMN #
0 1 28 29
30 31
0
1
13
14
CHARACTER ADDRESS BYTES
of DISPLAY REGISTERS
ROW
ATTRIBUTE
CRTL REG
R
E
S
E
R
V
E
D
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