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參數資料
| 型號： | MTV112M |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8051 Embedded CRT Monitor Controller Flash Version |
| 中文描述： | CRT顯示器8051嵌入式控制器Flash版本 |
| 文件頁數： | 15/20頁 |
| 文件大小： | 160K |
| 代理商： | MTV112M |
MYSON
TECHNOLOGY
MTV112M
(Rev 2.0)
Revision 2.0 - 15 - 2001/05/18
MBUF
(w) :
Master IIC data shift register, after START and before STOP condition, write this register will
resume MTV112M's transmission to the IIC bus.
MBUF
(r) :
Master IIC data shift register, after START and before STOP condition, read this register will
resume MTV112M's receiving from the IIC bus.
INTFLG
(w) :
Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt
enabler bit is set, the 8051 INT1 source will be driven by a zero level. Software MUST clear
this register while serving the interrupt routine.
= 1
→
No action.
= 0
→
Clears FIFOI flag.
= 1
→
No action.
= 0
→
Clears Master IIC bus interrupt flag (MI).
FIFOI
MI
INTFLG
(r) :
Interrupt flag.
= 1
FIFOI
→
Indicates the FIFO low condition; when EFIFO is set, MTV112M will be
interrupted by INT1.
→
Indicates when a byte is sent/received to/from the IIC bus; when EME is active,
MTV112M will be interrupted by INT1.
Interrupt enabler.
EFIFO = 1
→
Enables FIFO interrupt.
EMI
= 1
→
Enables Master IIC bus interrupt.
MI
= 1
INTEN
(w) :
FIFO
(w) :
Writes FIFO contents.
SLVCTR
(w) :
Slave IIC block control.
= 1
= 0
= 1
= 0
= 1
ESLVMI
ETXBI
ENSCL
ENSLV
→
Enables slave IIC block.
→
Disables slave IIC block.
→
Slave IIC connects to ISDA/ISCL.
→
Slave IIC connects to HSDA/HSCL.
→
Enables slave receiving buffer interrupt.
→
Enables slave address match interrupt.
→
Enables slave transmission buffer interrupt.
→
Enables slave block to hold SCL pin low.
SLVsel
ERCBI
= 1
= 1
= 1
SLVSTUS
(r) : Slave IIC block status.
WADR
SLVS
RCBI
SLVMI
= 1
= 1
= 1
= 1
→
The data in SLVBUF is a word address.
→
The slave block has detected a START; cleared when STOP detected.
→
RCBUF has loaded a new data byte; reset by S/W reading RCBUF.
→
The slave block has detected the slave address match condition; cleared
by S/W writing SLVSTUS.
→
TXBUF is empty; reset by S/W writing TXBUF.
→
Current transfer is slave transmitting.
→
Current transfer is slave receiving.
→
Master responds to NACK.
TXBI
RWB
= 1
= 1
= 0
= 1
ACKIN
SLVSTUS
(w) : Clears SLVMI flag.
RCBUF
(r) :
Slave IIC receives data buffer.
TXBUF
(w) :
Slave IIC transmits data buffer.
SLVADR
(w) : Slave IIC address to which the slave block should respond.
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