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參數資料
| 型號： | MV12030 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 80" Reco Smart Monolithic Microcomputer(語音存儲時間為80秒，單片智能微型電子計算機) |
| 中文描述： | 80“雷科智能單片機（語音存儲時間為80秒，單片智能微型電子計算機） |
| 文件頁數： | 6/12頁 |
| 文件大小： | 45K |
| 代理商： | MV12030 |
MV12030/12032
MOSEL VITELIC INC.
6/10
PID 258*** 05/98
Specifications subject to change without notice, contact your sales representatives for the most recent information.
Preliminary
Register Descriptions
MV12032 has 47 bytes secondary registers to handle
sophisticated peripherals. Most of them are 8-bit wide while some
of them has less than 8 bits defined. Because this is a dual output
channel chip, the register happens always in pair A/B. There are
4 I/O ports (each has 8 bits) for various interfacing with external
component(s).
They are described as below.
CRA, CRB
Control Registers A/B
Channel A and Channel B are controlled by their respective
register(s).
This register stores the execution bit of the melody/voice playing
through DAC. It also stores the control bit of cycling.
VA, VB
Volume Registers
Channel A and Channel B are controlled by their respective
register(s).
This 8-bit register controls the volume (loudness) of DAC output
when at tone mode.
SA, SB (SAL, SAM, SAH, SBL, SBM, SBH)
Start Address Registers A/B
Channel A and Channel B are controlled by their respective
register(s).
This 19-bit register stores the starting address of the melody/voice
waveform data to be played through DAC.
EA, EB (EAL, EAM, EAH, EBL, EBM, EBH)
End Address Registers A/B
Channel A and Channel B are controlled by their respective
register(s).
This 19-bit register stores the end address of the melody/voice
waveform data to be played through DAC.
SFA, SFB (SFAL, SFAH, SFBL, SFBH)
Sample Frequency Registers A/B
Channel A and Channel B are controlled by their respective
register(s).
This 16-bit register will serve to establish the sampling frequency
(sample rate, pitch) for each channel. It covers the range from
610 Hz to 20 MHz @ 40 MHz clock, working clock dependent.
The ADC uses the sample frequency set up by channel A.
DACA, DACB
DAC Registers A/B
Channel A and Channel B are controlled by their respective
register(s).
The ROM bytes are moved to these registers for conversion to
analog signals to drive the external speaker(s).
SR
Slow ROM Data Register
When accessing data ROM memory between 00100h - 7BFFFh,
this register will contain the valid data byte.
AT
Slow ROM Access Time Register
This 8-bit register represents the access time of the slow ROM.
P0, P1, P2, P3
I/O Port Data Registers
Each port has a data register. Writing a one to a bit in this register
causes the corresponding output port pin to switch high. Writing a
zero causes the output port pin to switch low. When used as an
input, the external state of a port pin will be held in the
corresponding data register.
DIR0, DIR1, DIR2, DIR3
I/O Port Direction Registers
Each port has a direction register. When set (=1) the port pin is an
output. When cleared (=0), the port pin in an input.
P0UD, P1UD, P2UD, P3UD
I/O Port Pull-Up/Pull-Down Control Registers
Each port has an Up/Down register.
Each bit configured as an input can also have a pull-up or
pull-down when the corresponding bit in the pull-up/pull-down
control register is set or cleared respectively.
P0EN, P1EN, P2EN, P3EN
I/O Port Pull-Up/Down Enable Registers
Each port has a Up/Down Enable register. It enables this option
for tie-off when the corresponding bit is set. It is disabled when
cleared.
POPT
Port Option Register
For port 0 and 1, several additional options are provided. This
register control those features : sleep, wake-up, mux channel,
watchdog timer, etc.
ADCH, ADCL
ADC Data Register
The result of analog-to-digital conversion is stored in 10-bit register.
The register is updated at the rate specified by the sampling
frequency from channel A. Content of this register are to be stored
in somewhere by the micro-controller.
ISL, ISH
Interrupt Status Register
This 9-bit register will indicate which source has triggered the INT1
signal of the micro-controller core.
IENL, IENH
Interrupt Enable Register
This 9-bit register enable/disable those 9-source to ISR register.
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