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參數(shù)資料
| 型號： | MV12032 |
| 廠商： | Mosel Vitelic, Corp. |
| 英文描述： | 80" ROMless Reco Smart Monolithic Microcomputer(語音存儲時間為80秒，無ROM單片智能微型電子計算機) |
| 中文描述： | 80“無ROM雷科單片機智能（語音存儲時間為80秒，無光盤單片智能微型電子計算機） |
| 文件頁數(shù)： | 3/12頁 |
| 文件大小： | 45K |
| 代理商： | MV12032 |
MV12030/12032
MOSEL VITELIC INC.
3/10
PID 258*** 05/98
Specifications subject to change without notice, contact your sales representatives for the most recent information.
Preliminary
Block Descriptions
MV12032 has 10-some major blocks built in.
They are described as below.
U2052 Core
This is a commercial 8052 compatible core circuit block with some
redundant component prunned. All the instruction is compatible to
commercial 8052's.
There is 384 bytes 8052's register built in. 8 K bytes program
ROM is provided inside as well.
Secondary Registers
(176 bytes)
There are 47 bytes registers provided to give programmer ability to
acess far beyond the commercial 8052 can reach. They are
located at the data address 050h through 0FFh. Some of them
are write-only while some of them are read-only. Some of them
are able to read and write.
The details are listed in following pages.
Data ROM
(496 KB)
This is a huge data block to store either voice/melody data or misc
data. To match the speed difference between CPU and ROM, a
data latch register SRR is provided.
It could be accessed either by melody play mechanism or CPU
core.
Below figure shows the relationship between it and melody play
mechanism.
SRAM
(16 KB)
This is a data read/write area with competitive access speed as
CPU's.
I/O Ports
(8 bits x 4)
Each bit can be one state out of these 5 : output-low, output-high,
input-pull-low, input-pull-high and input-floating. Each bit each
port could be accessed independently.
It could wake up the sleeping MV12032 by applying an activation
to any bit of port 0.
There are 16 registers pertinent to these 4 ports, 4 per port - data,
direction, up/down and pull-enable.
Interrupt Manipulator
It accepts 9 interrupt sources. Some of them are from external
while some are from internal.
The internal interrupts are melody accomplishment (A & B), pitch
generator (A & B), watchdog timer, AD converter, Data ROM valid,
external event and test mode.
All these interrupts could be disable or enable bitwise when running
in program.
Watch Dog Timer
The CPU core will be given an interrupt from this watchog every
specified interval or the CPU will be reset.
Reset Circuit
The reset circuit could generate system demanded reset signal
while accepting activation or internal event.
Its threshold is mask option as well.
DACs
(8 bits x 2)
It could be controlled by both loudness (volume) register and pitch
(sample rate) register. Both loudness and pitch registers are
programmable.
By the mechanism of CRA, VA, SA, EA, SFA and DACA registers,
the melody/voice could be played. Left bottom figure shows the
mechanism.
start addr.
register S
end addr.
register E
Data access circuit
cycle
flag bit
run
flag bit
496KB
Data
ROM
ADC
sample rate
gener'r. A
POPT
register
4-to-1
MUX
loudness
control
sample rate
generator
DAC
Data
Latch
ADC
(10 bits, 4 channel)
It is used when recording audio to store in data memory. It is
composed of an analog mux, an AGC block and an analog to digital
converter. The sampled signal is digitized at 10 bit resolution at
sample rate from channel A and stored in data register ADCH/L.
The 4 channels could be specified by bits in POPT.
to
data
latch
of DAC
to
inter'pt
SRR
to interrupt
to
CPU
from
pins
CHn
Data reg'r.
ADCH/L
register
V
register
SF
from
data access ckt.
from
CPU
to
external
AUA/B
to
inter'pt
to
inter'pt
to CPU
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