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參數資料
| 型號： | N150X4-L01 |
| 廠商： | Standard Power |
| 英文描述： | Engineering Specification Type 15.0 XGA Color TFT/LCD Module |
| 中文描述： | 工程規格型號15.0 XGA彩色液晶/液晶顯示模塊 |
| 文件頁數： | 12/29頁 |
| 文件大小： | 147K |
| 代理商： | N150X4-L01 |
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EEDID Data
Data
EEDID
Note :
Output signals except V
EEDID
, CLK
EEDID
and Data
EEDID
from any system shall be Hi-Z state when VDD is
off.
EEDID Clock
CLK
EDID
EEDID 3.3 V Power Supply
V
EEDID
Ground
GND
Power Supply
VDD
Horizontal Sync:The signal is synchronized with DTCLK . Both active high/low
signals are acceptable.
HSYNC(H-S)
Vertical Sync:The signal is synchronized to DTCLK . Both active high/low
signal acceptable.
VSYNC(V-S)
When the signal is high, the pixel data shall be valid to be displayed.
+DSPTMG(DSP)
Data Clock:The typical frequency is 65.0 MHz.
The signal is used to strobe the pixel data and the DSPTMG .
DTCLK
Blue Data 5 (MSB)
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0 (LSB)
Blue-pixel Data: Each blue pixel's brightness data consists of these 6 bits pixel data.
+BLUE 5
+BLUE 4
+BLUE 3
+BLUE 2
+BLUE 1
+BLUE 0
Green Data 5 (MSB)
Green Data 4
Green Data 3
Green Data 2
Green Data 1
Green Data 0 (LSB)
Green-pixel Data: Each green pixel's brightness data consists of these 6 bits pixel data.
+GREEN 5
+GREEN 4
+GREEN 3
+GREEN 2
+GREEN 1
+GREEN 0
Red Data 5 (MSB)
Red Data 4
Red Data 3
Red Data 2
Red Data 1
Red Data 0 (LSB)
Red-pixel Data: Each red pixcel's brightness data consists of these 6 bits pixel data.
+RED5
+RED4
+RED3
+RED2
+RED1
+RED0
Description
SIGNAL NAME
Engineering Specification
(C) Copyright International Display Technology 2002 All Rights reserved.
February 06,2003
OEM N150X4-L01-01
12/29
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