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參數(shù)資料
| 型號： | NB3N108KMNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FANOUT BUFFER 1:8 HCSL 32QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 扇出緩沖器（分配），數(shù)據(jù) |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:8 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | HCSL, LVCMOS, LVDS, LVPECL, LVTTL |
| 輸出： | HCSL，LVDS |
| 頻率 - 最大： | 400MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 6
1
Publication Order Number:
NB3N108K/D
NB3N108K
3.3V Differential 1:8 Fanout
Clock Data Driver with
HCSL Outputs
Description
The NB3N108K is a differential 1:8 Clock fanout buffer with
Highspeed Current Steering Logic (HCSL) outputs optimized for
ultra low propagation delay variation. The NB3N108K is designed
with HCSL PCI Express clock distribution and FBDIMM
applications in mind.
Inputs can directly accept differential LVPECL, LVDS, HCSL
LVCMOS, or LVTTL levels are accepted with a proper external Vth
internal 50
W termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475
W resistor from IREF
(Pin 1) to GND per Figure 6. Outputs can also interface to LVDS
receivers when terminated per Figure 11.
The NB3N108K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB3N108K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, or 400 MHz
220 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation Per Each Diff
Pair
0.1 ps Typical Integrated Phase Jitter RMS
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Differential HCSL Output Levels
LVDS Output Levels with Interface Termination
These are PbFree Devices
Applications
Clock Distribution
PCIe I, II, III
Networking and Communications
High End Computing
Routers
End Products
Servers
FBDIMM Memory Card
Ethernet Switch/Routers
*For additional marking information, refer to
Application Note AND8002/D.
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
http://onsemi.com
Figure 1. Simplified Logic Diagram
Q0
Q1
Q6
Q7
CLK
VCC
GND
RREF
IREF
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
VTCLK
32
1
NB3N
108K
AWLYYWWG
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB3N111KMNG | 功能描述:時鐘緩沖器 1:10 HCSL FAN-OUT BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| NB3N111KMNR4G | 功能描述:時鐘緩沖器 1:10 HCSL FAN-OUT BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| NB3N1200K | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle |
| NB3N1200KMNG | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle |
| NB3N1200KMNTXG | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle |
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