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參數資料
| 型號： | NB6L295MNGEVB |
| 廠商： | ON Semiconductor |
| 文件頁數： | 11/13頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL NB6L295MN CLK DELAY |
| 標準包裝： | 1 |
| 主要目的： | 計時，時鐘分配 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | NB6L295 |
| 次要屬性： | SMA 連接器 |
| 已供物品： | 板 |
| 其它名稱： | NB6L295MNGEVB-ND NB6L295MNGEVBOS |
NB6L295
http://onsemi.com
7
Serial Data Interface Programming
The NB6L295 is programmed by loading the 11Bit SHIFT REGISTER using the SCLK, SDATA and SLOAD inputs. The
11 SDATA bits are 1 PSEL bit, 1 MSEL bit and 9 delay value data bitsD[8:0]. A separate 11bit load cycle is required to program
the delay data value of each channel, PD0 and PD1. For example, at powerup two load cycles will be needed to initially set
PD0 and PD1; Dual Mode Operation as shown in Figures 3 and 4 and Extended Mode Operation as shown in Figures 5 and 6.
DUAL MODE OPERATIONS
PD0 Programmable Delay
Control
Bits
Value
PD1 Programmable Delay
Control
Bits
Value
0/1
0
0/1
0
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL PSEL Bit
Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL PSEL Bit
Name
(MSB)
(LSB)
Name
(MSB)
(LSB)
Name
Figure 3. PDO Shift Register
Figure 4. PD1 Shift Register
EXTENDED MODE OPERATIONS
PD0 Programmable Delay
Control
Bits
Value
PD1 Programmable Delay
Control
Bits
Value
0/1
1
0
0/1
1
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL PSEL Bit
Name
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSEL PSEL Bit
Name
(MSB)
(LSB)
Name
(MSB)
(LSB)
Name
Figure 5. PDO Shift Register
Figure 6. PD1 Shift Register
Refer to Table 6, Channel and Mode Select BIT Functions. In a load cycle, the 11Bit Shift Register least significant bit
(clocked in first) is PSEL and will determine which channel delay buffer, either PDO (LOW) or PD1 (HIGH), will latch the
delay data value D[8:0]. The MSEL BIT determines the Delay Mode. When set LOW, the Dual Delay Mode is selected and
the device uses both channels independently. A pulse edge entering IN0/IN0 is delayed according to the values in PD0 and exits
from Q0/Q0. An input signal pulse edge entering IN1/IN1 is delayed according to the values in PD1 and exits from Q1/Q1.
When MSEL is set HIGH, the Extended Delay Mode is selected and an input signal pulse edge enters IN0 and IN0 and flows
through PD0 and is extended through PD1 to exit at Q1 and Q1. The most significant 9bits, D[8:0] are delay value data for
both channels. See Figure 7.
Table 6. CHANNEL AND MODE SELECT BIT FUNCTIONS
BIT Name
Function
PSEL
0 Loads Data to PD0
1 Loads Data to PD1
MSEL
0 Selects Dual Programmable Delay Paths, 3.1 ns to 8.8 ns Delay Range for Each Path
1 Selects Extended Delay Path from IN0/IN0 to Q1/Q1, 6.0 ns to 17.2 ns Delay Range; Disables Q0/Q0 Outputs,
Q0LOW, Q0HIGH.
D[8:0]
Select one of 512 Delay Values
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相關代理商/技術參數 |
參數描述 |
|---|---|
| NB6L295MNTXG | 功能描述:延遲線/計時元素 LVPECL DUAL PRG DLAY RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 傳播延遲時間:1000 ps 工作溫度范圍: 封裝 / 箱體:QFN-24 封裝:Tube |
| NB6L56MNG | 功能描述:時鐘緩沖器 TSMC 2.5V/3.3V DUAL DIFF RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| NB6L56MNTXG | 功能描述:時鐘緩沖器 2.5V/3.3V DUAL DIFFERENTI RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| NB6L572M | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator |
| NB6L572MMNG | 功能描述:編碼器、解碼器、復用器和解復用器 ANA 500MA ANY CAP LDO RoHS:否 制造商:Micrel 產品:Multiplexers 邏輯系列:CMOS 位數: 線路數量（輸入/輸出）:2 / 12 傳播延遲時間:350 ps, 400 ps 電源電壓-最大:2.625 V, 3.6 V 電源電壓-最小:2.375 V, 3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-44 封裝:Tray |
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