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參數(shù)資料
| 型號： | NB6LQ572MNR4G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK MUX TRANSLA 4:2 32-QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 系列： | ECLinPS MAX™ |
| 類型： | 多路復(fù)用器，變換器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 4:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 5GHz |
| 電源電壓： | 2.375 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-QFN（5x5） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2009
April, 2009 Rev. 0
1
Publication Order Number:
NB6LQ572/D
NB6LQ572
2.5V / 3.3V Differential 4:1
Mux w/Input Equalizer to
1:2 LVPECL Clock/Data
Fanout / Translator
MultiLevel Inputs w/ Internal Termination
The NB6LQ572 is a high performance differential 4:1 Clock/Data
input multiplexer and a 1:2 LVPECL Clock / Data fanout buffer that
operates up to 5 GHz / 6.5 Gbps respectively with a 2.5 V or 3.3 V
power supply.
Each INx/INx input pair incorporates a fixed Equalizer Receiver,
which when placed in series with a Clock / Data path, will enhance the
degraded signal transmitted across an FR4 backplane or cable
interconnect. For applications that do not require Equalization,
consider the NB6L572, which is pincompatible to the NB6LQ572.
The differential Clock / Data inputs have internal 50
W termination
resistors and will accept differential LVPECL, CML, or LVDS logic
levels. The NB6LQ572 incorporates a pair of Select pins that will
choose one of four differential inputs and will produce two identical
LVPECL output copies of Clock or Data. As such, the NB6LQ572 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The two differential LVPECL outputs will swing 750 mV when
externally loaded and terminated with a 50
W resistor to VCC – 2 V
and are optimized for low skew and minimal jitter.
The NB6LQ572 is offered in a low profile 5x5 mm 32pin QFN
PbFree package. Application notes, models, and support
documentation are available at www.onsemi.com.
The NB6LQ572 is a member of the ECLinPS MAX
family of
high performance clock products.
Features
Input Data Rate > 6.5 Gb/s Typical
Data Dependent Jitter < 10 ps
Maximum Input Clock Frequency > 5 GHz Typical
Random Clock Jitter < 0.8ps RMS
Fixed Input Equalization
Low Skew 1:2 LVPECL Outputs, < 15 ps max
4:1 MultiLevel Mux Inputs, accepts LVPECL, CML LVDS
150ps Typical Propagation Delay
55ps Typical Rise and Fall Times
Differential LVPECL Outputs, 800 mV peaktopeak, typical
Operating Range: VCC = 2.375 V to 3.6 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5mm x 5mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 9 of
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
32
1
NB6L
Q572
AWLYYWWG
G
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
(Note: Microdot may be in either location)
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相關(guān)代理商/技術(shù)參數(shù) |
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| NB6MAAH0-0-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:N e u t r i k ?? P a r t N u m b e r G u i d e |
| NB6MAH0-0-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:N e u t r i k ?? P a r t N u m b e r G u i d e |
| NB6N11S | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3 V 1:2 AnyLevel TM Input to LVDS Fanout Buffer /Translator |
| NB6N11S_06 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3 V 1:2 AnyLevel TM Input to LVDS Fanout Buffer /Translator |
| NB6N11SMNG | 功能描述:時鐘緩沖器 NSEB THAI TRANS RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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