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參數資料
型號: NB7HQ14MMNTXG
廠商: ON Semiconductor
文件頁數: 1/10頁
文件大小: 0K
描述: IC CLK/DATA BUFFER MUX 1:4 16QFN
標準包裝: 3,000
系列: GigaComm™
類型: 扇出緩沖器(分配),多路復用器,數據
電路數: 1
比率 - 輸入:輸出: 1:4
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: CML
頻率 - 最大: 7GHz
電源電壓: 2.375 V ~ 2.625 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應商設備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2009
May, 2009 Rev. 0
1
Publication Order Number:
NB7HQ14M/D
NB7HQ14M
2.5V 7GHz / 10Gbps
Differential Input to 1.8V /
2.5V 1:4 CML Clock / Data
Fanout Buffer w/ Selectable
Input Equalizer
MultiLevel Inputs w/ Internal Termination
Description
The NB7HQ14M is a high performance differential 1:4 CML fanout
buffer with a selectable Equalizer receiver. When placed in series with
a Clock /Data path operating up to 7 GHz or 10 Gb/s, respectively, the
NB7HQ14M inputs will compensate the degraded signal transmitted
across a FR4 PCB backplane or cable interconnect and output four
identical CML copies of the input signal. Therefore, the serial data rate
is increased by reducing InterSymbol Interference (ISI) caused by
losses in copper interconnect or long cables. The EQualizer ENable
pin (EQEN) allows the IN/IN inputs to either flow through or bypass
the Equalizer section. Control of the Equalizer function is realized by
setting EQEN; When EQEN is set Low, the IN/IN inputs bypass the
Equalizer. When EQEN is set High, the IN/IN inputs flow through the
Equalizer. The default state at startup is LOW. As such, NB7HQ14M
is ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The differential inputs incorporate internal 50
W termination
resistors that are accessed through the VT pin. This feature allows the
NB7HQ14M to accept various logic level standards, such as LVPECL,
CML or LVDS. The outputs have the flexibility of being powered by
either a 2.5 V or 1.8 V supply. The 1:4 fanout design was optimized
for low output skew applications.
The NB7HQ14M is a member of the GigaComm
family of high
performance clock products.
Features
Input Data Rate > 10 Gb/s
Input Clock Frequency > 7 GHz
150 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
< 15 ps Maximum Output Skew
< 0.8 ps Maximum RMS Clock Jitter
< 10 ps pp of Data Dependent Jitter
Differential CML Outputs, 400 mV PeaktoPeak, Typical
Selectable Input Equalization
Operating Range: VCC = 2.375 V to 2.625 V, VCCO = 1.71 V to
2.625 V
Internal Input Termination Resistors, 50 W
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
QFN16
MN SUFFIX
CASE 485G
16
NB7H
Q14M
ALYWG
G
1
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
1
EQ
SIMPLIFIED BLOCK DIAGRAM
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NB7L1008MMNR4G 功能描述:時鐘緩沖器 TSMC 1:8 F/O MLL-CML RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲(最大值): 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
NB7L1008MMNTWG 制造商:ON Semiconductor 功能描述:TSMC 1:8 F/O MLL-CML - Tape and Reel
NB7L111M 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:2.5V / 3.3V, 6.125Gb/s 1:10 Differential Clock/Data Driver with CML Output
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