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參數資料
型號: NB7L11MMNR2G
廠商: ON Semiconductor
文件頁數: 1/11頁
文件大小: 0K
描述: IC CLK/DTA BUF TRNSLA 1:2 16-QFN
標準包裝: 3,000
類型: 扇出緩沖器(分配),變換器,數據
電路數: 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 是/是
輸入: CML,LVCMOS,LVDS,LVPECL,LVTTL
輸出: CML
頻率 - 最大: 8GHz
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應商設備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2011
January, 2011 Rev. 3
1
Publication Order Number:
NB7L11M/D
NB7L11M
2.5V/3.3V Differential 1:2
Clock/Data Fanout Buffer/
Translator with CML
Outputs and Internal
Termination
Description
The NB7L11M is a differential 1to2 clock/data distribution chip
with internal source termination and CML output structure, optimized
for low skew and minimal jitter. The device is functionally equivalent to
the EP11, LVEP11, or SG11 devices. Device produces two identical
output copies of clock or data operating up to 8 GHz or 12 Gb/s,
respectively. As such, NB7L11M is ideal for SONET, GigE, Fiber
Channel, Backplane and other clock/data distribution applications.
Inputs incorporate internal 50
W termination resistors and accept
LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6).
Differential 16 mA CML output provides matching internal 50
W
terminations, and 400 mV output swings when externally terminated,
50
W to VCC (See Figure 14).
The device is offered in a low profile 3x3 mm 16pin QFN package.
Application notes, models, and support documentation are available at
www.onsemi.com.
Features
Maximum Input Clock Frequency up to 8 GHz Typical
Maximum Input Data Rate up to 12 Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 10 ps of Data Dependent Jitter
30 ps Typical Rise and Fall Times
110 ps Typical Propagation Delay
3 ps Typical Within Device Skew
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV PeaktoPeak Output) Differential
Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP
and SG Devices
PbFree Packages are Available
Figure 1. Logic Diagram
Q0
Q1
VTCLK
CLK
VTCLK
50 W
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
NB7L
11M
ALYWG
G
1
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