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參數資料
型號: NB7L32MMNR2G
廠商: ON Semiconductor
文件頁數: 1/10頁
文件大小: 0K
描述: IC CLOCK DIVIDER 1:2 16-QFN
標準包裝: 3,000
類型: 時鐘除法器
PLL:
輸入: CML,ECL,LVDS,LVPECL
輸出: CML
電路數: 1
比率 - 輸入:輸出: 1:1
差分 - 輸入:輸出: 是/是
頻率 - 最大: 14GHz
除法器/乘法器: 是/無
電源電壓: 2.375 V ~ 3.465 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應商設備封裝: 16-QFN(3x3)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2011
January, 2011 Rev. 3
1
Publication Order Number:
NB7L32M/D
NB7L32M
2.5V/3.3V, 14GHz ÷2 Clock
Divider w/CML Output and
Internal Termination
Description
The NB7L32M is an integrated
÷2 divider with differential clock
inputs and asynchronous reset.
Differential clock inputs incorporate internal 50
W termination
resistors and accept LVPECL (Positive ECL), CML, or LVDS. The
high frequency reset pin is asserted on the rising edge. Upon
powerup, the internal flipflops will attain a random state; the reset
allows for the synchronization of multiple NB7L32M’s in a system.
The differential 16 mA CML output provides matching internal
50
W termination which guarantees 400 mV output swing when
externally receiver terminated 50
W to VCC (See Figure 15).
The device is housed in a small 3x3 mm 16 pin QFN package.
Features
Maximum Input Clock Frequency 14 GHz Typical
200 ps Max Propagation Delay
30 ps Typical Rise and Fall Times
< 0.5 ps Maximum (RMS) Random Clock Jitter
Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
CML Output Level (400 mV PeaktoPeak Output), Differential
Output Only
50 W Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
EP, and SG Devices
These are PbFree Devices
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
VTCLK
CLK
VTCLK
50 W
Q
Divide by 2
Reset
R
VEE
R1
FUNCTIONAL BLOCK DIAGRAM
VCC
CLK
TRUTH TABLE
xx
H
ZW
L
CLK
R
QQ
L
÷2
H
Z = LOW to HIGH Transition
W = HIGH to LOW Transition
x = Don’t Care
16
NB7L
32M
ALYWG
G
1
1
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