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參數(shù)資料
型號: NB7L585MNR4G
廠商: ON Semiconductor
文件頁數(shù): 1/9頁
文件大小: 0K
描述: IC CLK/DATA BUFFER MUX 1:6 32QFN
標準包裝: 1,000
系列: GigaComm™
類型: 扇出緩沖器(分配),多路復用器,數(shù)據(jù)
電路數(shù): 1
比率 - 輸入:輸出: 1:6
差分 - 輸入:輸出: 是/是
輸入: CML,LVDS,LVPECL
輸出: LVPECL
頻率 - 最大: 5GHz
電源電壓: 2.375 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應商設備封裝: 32-QFN(5x5)
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2009
December, 2009 Rev. 1
1
Publication Order Number:
NB7L585/D
NB7L585
2.5V / 3.3V Differential 2:1
Mux Input to 1:6 LVPECL
Clock/Data Fanout Buffer /
Translator
MultiLevel Inputs w/ Internal
Termination
Description
The NB7L585 is a differential 1:6 LVPECL Clock/Data distribution
chip featuring a 2:1 Clock/Data input multiplexer with an input select
pin. The INx/INx inputs incorporate internal 50
W termination
resistors and will accept LVPECL, CML, or LVDS logic levels.
The NB7L585 produces six identical output copies of Clock or Data
operating up to 5 GHz or 8 Gb/s, respectively. As such, NB7L585 is
ideal for SONET, GigE, Fiber Channel, Backplane and other
Clock/Data distribution applications.
The NB7L585 is powered with either 2.5 V or 3.3 V supply and is
offered in a low profile 5mm x 5mm 32pin QFN package.
Application notes, models, and support documentation are available
at www.onsemi.com.
The NB7L585 is a member of the GigaComm
family of high
performance clock products.
Features
Maximum Input Data Rate > 8 Gb/s
Data Dependent Jitter < 15 ps
Maximum Input Clock Frequency > 5 GHz
Random Clock Jitter < 0.8 ps RMS
Low Skew 1:6 LVPECL Outputs, 20 ps max
2:1 MultiLevel Mux Inputs
175 ps Typical Propagation Delay
55 ps Typical Rise and Fall Times
Differential LVPECL Outputs, 800 mV peaktopeak, typical
Operating Range: VCC = 2.375 V to 3.6 V with GND = 0 V
Internal 50 W Input Termination Resistors
VREFAC Reference Output
QFN32 Package, 5mm x 5mm
40C to +85C Ambient Operating Temperature
These Devices are PbFree and are RoHS Compliant
QFN32
MN SUFFIX
CASE 488AM
See detailed ordering and shipping information on page 8 of
this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAM
http://onsemi.com
32
1
NB7L
585
AWLYYWWG
G
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
(Note: Microdot may be in either location)
50 W
IN1
VT1
IN1
50 W
IN0
VT0
IN0
Figure 1. Simplified Block Diagram
0
1
VREFAC1
VREFAC0
Q0
Q1
Q2
Q3
Q4
Q5
VCC
GND
+
SEL
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