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參數資料
| 型號： | NB7L86MMN |
| 廠商： | ON Semiconductor |
| 文件頁數： | 9/12頁 |
| 文件大小： | 0K |
| 描述： | IC GATE MULTI FUNCT DIFF 16-QFN |
| 產品變化通告： | LTB Notification 06/Feb/2008 |
| 標準包裝： | 123 |
| 邏輯類型： | 可配置多功能 |
| 電路數： | 2 |
| 輸入數： | 2 |
| 施密特觸發器輸入： | 無 |
| 輸出類型： | 差分 |
| 電源電壓： | 2.4 V ~ 3.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 16-QFN（3x3） |
| 包裝： | 管件 |
NB7L86M
http://onsemi.com
6
Symbol
Characteristic
40_C
25_C
85_C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
VOUTPP Output Voltage Amplitude (@VINPPmin)fin ≤ 4 GHz
(See Figure 7)
fin ≤ 8 GHz
240
125
350
230
240
125
350
230
240
125
350
230
mV
fdata
Maximum Operating Data Rate
10.7
12
10.7
12
10.7
12
Gb/s
tPLH,
tPHL
Propagation Delay to
Dx/Dx to Q/Q
Output Differential @ 1 GHz
SEL/SEL to Q/Q
(See Figure 7)
70
110
90
135
120
180
70
110
90
135
120
180
70
110
90
135
120
180
ps
tSKEW
Duty Cycle Skew (Note 14)
DevicetoDevice Skew (Note 15)
2.0
5.0
10
20
2.0
5.0
10
20
2.0
5.0
10
20
ps
tS
SetUp Time (Dx to SEL)
100
ps
tH
HoldUp Time (Dx to SEL)
15
ps
tJITTER
RMS Random Clock Jitter (Note 16)
fin = 4 GHz
fin =8 GHz
Peak/Peak Data Dependent Jitter
fdata = 5 Gb/s
(Note 17)
fdata =10 Gb/s
0.2
2.0
4.0
0.5
8.0
10
0.2
2.0
4.0
0.5
8.0
10
0.2
2.0
4.0
0.5
8.0
10
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 18)
75
400
2500
75
400
2500
75
400
2500
mV
tr
tf
Output Rise/Fall Times @ 1 GHz
Q, Q
(20% 80%)
35
60
35
60
35
60
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board
with maintained airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range.
Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually
under normal operating conditions and not valid simultaneously.
13.Measured by forcing VINPP (TYP) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC.
Input edge rates 40 ps (20% 80%).
14.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @1 GHz.
15.Device to device skew is measured between outputs under identical transition @ 1 GHz.
16.Additive RMS jitter with 50% duty cycle clock signal.
17.Additive peaktopeak data dependent jitter with input NRZ data (PRBS 2^231).
18.VINPP (MAX) cannot exceed VCC VEE. Input voltage swing is a singleended measurement operating in differential mode.
INPUT FREQUENCY (GHz)
Figure 7. Output Voltage Amplitude (VOUTPP) versus
Input Clock Frequency (fin) at Ambient Temperature (Typical)
OUTPUT
VOL
TAGE
AMPLITUDE
(mV)
500
400
300
200
100
0
12
11
10
9
8
7
6
5
4
3
2
1
0
VCC VEE = 3.3 V
VCC VEE = 2.5 V
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