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參數資料
| 型號： | NB7N017MMNR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 諧振器 |
| 英文描述： | 3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs |
| 中文描述： | 7N SERIES, PRESCALER, QCC52 |
| 封裝： | 8 X 8 MM, QFN-52 |
| 文件頁數： | 10/20頁 |
| 文件大小： | 177K |
| 代理商： | NB7N017MMNR2 |
NB7N017M
http://onsemi.com
10
Table 11. AC CHARACTERISTICS
V
CC
= 0 V; V
EE
=
3.465 V to
3.0 V or V
CC
= 3.0 V to 3.465 V; V
EE =
0 V (Note 19)
40
°
C
25
°
C
85
°
C
Symbol
V
OUTPP
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
mV
Output Voltage Amplitude @
2 Mode
f
in
= 3.5 GHz
(See Figure 5)
300
400
300
400
300
400
t
PLH
,
t
PHL
Propagation Delay to Output Differential
CLK to TC
MR to TC
435
100
555
500
455
100
575
500
475
100
595
500
ps
t
JITTER
RMS Random Clock Jitter f
in
= 3.5 GHz
(See Figure 5)
2.5
3.0
3.0
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 20)
100
2500
100
2500
100
2500
mV
t
r
t
f
Output Rise/Fall Times
(20%
80%)
25
45
65
25
45
65
25
45
65
ps
t
s
Setup Time
(Figure 23)
Pa[7:0] to PLa
Pb[7:0] to PLb
CE to CLK
SEL to CLK
PLa to CLK
PLb to CLK
Pa[7:0] to CLK
Pb[7:0] to CLK
3750
4500
400
300
2500
3250
4750
3000
2500
2000
30
120
2000
2750
3500
2500
3750
4500
400
300
2500
3250
4750
3000
2500
2000
30
120
2000
2750
3500
2500
3750
4500
400
300
2500
3250
4750
3000
2500
2000
30
120
2000
2750
3500
2500
ps
t
H
Hold Time
(Figure 23)
PLa to Pa[7:0]
PLb to Pb[7:0]
CLK to CE
CLK to SEL
CLK to PLa
CLK to PLb
CLK to PLb[7:0]
CLK to PLb[7:0]
1500
1250
450
0
1750
2250
2250
2000
2700
1900
40
110
1900
2700
3200
2500
1500
1250
450
0
1750
2250
2250
2000
2700
1900
40
110
1900
2700
3200
2500
1500
1250
450
0
1750
2250
2250
2000
2700
1900
40
110
1900
2700
3200
2500
ps
t
SKEW
t
PW
t
RR
Device
to
Device (Note 21)
40
75
40
75
40
75
ps
Minimum Pulse Width
MR
250
85
250
85
250
85
ps
Reset Recovery
MR to TC
3000
2500
3000
2500
3000
2500
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating
temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are
applied individually under normal operating conditions and not valid simultaneously.
19.Measured using a 400 mV source, 50% duty cycle clock source at f
in
= 1 GHz unless stated otherwise. All loading with 50 to V
CC
. Input edge
rates 40 ps (20%
80%).
20.V
INPP
(MAX) cannot exceed V
CC
V
EE
.
21.Device
to
Device skew for identical transitions at identical V
CC
levels.
INPUT FREQUENCY (MHz)
Figure 5. Output Voltage Amplitude (V
OUTPP
) / RMS Jitter vs. Input Frequency (f
in
)
@ Ambient Temperature (Typical)
O
J
O
0
100
200
300
400
0
0.5
1
1.5
2
2.5
3
3.5
4
0
1
2
3
4
V
OUTPP
RMS Jitter
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