參數資料
| 型號： | NB7N017MMNR2G |
| 廠商： | ON Semiconductor |
| 文件頁數： | 1/19頁 |
| 文件大小： | 0K |
| 描述： | IC DIVIDER 8BIT DUAL CML 52-QFN |
| 標準包裝： | 2,000 |
| 類型： | 時鐘除法器 |
| PLL： | 無 |
| 輸入： | CML，ECL，LVCMOS，LVDS，LVTTL |
| 輸出： | CML |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 3.5GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | ±3 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 52-QFN（8x8） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2012
January, 2012 Rev. 4
1
Publication Order Number:
NB7N017M/D
NB7N017M
3.3V SiGe 8-Bit Dual
Modulus Programmable
Divider/Prescaler with CML
Outputs
The NB7N017M is a high speed 8–bit dual modulus
programmable divider/prescaler with 16 mA CML outputs capable
of switching at input frequencies greater than 3.5 GHz. The CML
output structure contains internal 50
W source termination resistor to
VCC. The device generates 400 mV output amplitude with 50 W
receiver resistor to VCC. This I/O structure enables easy
implementation of the NB7N017M in 50
W systems.
The differential inputs contain 50
W termination resistors to VT
pads and all differential inputs accept RSECL, ECL, LVDS,
LVCMOS, LVTTL, and CML.
Internally, the NB7N017M uses a > 3.5 GHz 8–bit programmable
down counter. A select pin, SEL, is used to select between two
words, Pa[0:7] and Pb[0:7], that are stored in REGa and REGb
respectively. Two parallel load pins, PLa and PLb, are used to load
the level triggered programming registers, REGa and REGb,
respectively. A differential clock enable, CE, pin is available.
The NB7N017M offers a differential output, TC. Terminal count
output, TC, goes high for one clock cycle when the counter has
reached the all zeros state. To reduce output phase noise, TC is
retimed with the rising edge triggered latches.
Features
Maximum Input Clock Frequency > 3.5 GHz Typical
Differential CLK Clock Input
Differential CE Clock Enable Input
Differential SEL Word Select Input
50 W Internal Input and Output Termination Resistors
Differential TC Terminal Count Output
All Outputs 16 mA CML with 50 W Internal Source Termination
to VCC
All Single–Ended Control Pins CMOS and PECL/NECL
Compatible
Counter Programmed Using One of Two SingleEnded Words,
Pa[0:7] and Pb[0:7], Stored in REGa and REGb
REGa and REGb Implemented with Level Triggered Latch
Compatible with Existing 3.3 V LVEP, EP, and SG Devices
Ability to Program the Divider without Disturbing Current Settings
Positive CML Output Operating Range: VCC = 3.0 V to 3.465 V
with VEE = 0 V
Negative CML Output Operating Range: VCC = 0 V
with VEE = –3.0 V to –3.465 V
VBB Reference Voltage Output
CML Output Level: 400 mV PeakPeak Output with 50 W Receiver
Resistor to VCC
PbFree Packages are Available*
A
= Assembly Site
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
QFN52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
ORDERING INFORMATION
*For additional information on our PbFree strategy
and soldering details, please download the ON Semi-
conductor Soldering and Mounting Techniques Ref-
erence Manual, SOLDERRM/D.
NB7N
017M
AWLYYWWG
1
52
152
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