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參數資料
型號: NB7N017MMNR2G
廠商: ON SEMICONDUCTOR
元件分類: 諧振器
英文描述: 3.3V SiGe 8-Bit Dual Modulus Programmable Divider/Prescaler with CML Outputs
中文描述: 7N SERIES, PRESCALER, QCC52
封裝: 8 X 8 MM, LEAD FREE, QFN-52
文件頁數: 3/20頁
文件大小: 177K
代理商: NB7N017MMNR2G
NB7N017M
http://onsemi.com
3
Table 1. PIN DESCRIPTION
Pin Name
I/O
Default
State
Single/Differential
(Notes 1 and 2)
Description
CLK
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Differential
Clock
CE
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Differential
Clock Enable
MR
CMOS, ECL Input
Low
Single
Asynchronous Master Reset: Counter set to 0000 0000 to
reload at next CLK pulse, REGa and REGb = 1111 1111 and
TC = 1.
SEL
ECL, CML, LVCMOS,
LVDS, LVTTL Input
Differential
Divide Select
PLa, PLb
CMOS, ECL Input
Low
Single
Parallel Load Counter Latch from Pa[0:7], Pb[0:7] (Level
Triggered)
TC
CML Output
Differential
Terminal Count, 16 mA CML output with 50 Source
Termination to V
CC
(Note 5)
Pa[0:7], Pb[0:7]
CMOS, ECL Input
High
Single
Counter Program Pins. CMOS and PECL/NECL compatible
Pa7 = MSB, Pb7 = MSB
V
CC
Power
Positive Supply
V
EE
Power
Negative Supply
VTCLK, VTCLK,
VTSEL, VTSEL
VTCE, VTCE
Termination
Differential
50 Internal Input Termination Resistor (Note 6)
V
BB
Output
CMOS/ECL Reference Voltage Output
NC
N/A
No Connect (Note 4)
2. All single
ended inputs are CMOS and NECL/ECL compatible.
3. All V
CC
and V
EE
pins must be externally connected to external power supply voltage to guarantee proper device operation. The thermally
exposed pad (EP) on package bottom (see case drawing) must be attached to a heat
sinking conduit. Exposed pad is bonded to the lowest
voltage potential, V
EE
.
4. The NC pins are electrically connected to the die and must be left open.
5. CML outputs require 50 receiver termination resistor to V
CC
for proper operation.
6. In the differential configuration when the input termination pins are connected to the common termination voltage, and if no signal is applied
then the device will be susceptible to self
oscillation.
Exposed Pad (Note 3)
相關PDF資料
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