參數資料
| 型號： | NB7V32MMNTXG |
| 廠商： | ON Semiconductor |
| 文件頁數： | 1/9頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK DIVIDER 1.8/2.5V 16-QFN |
| 標準包裝： | 3,000 |
| 系列： | GigaComm™ |
| 類型： | 時鐘除法器 |
| PLL： | 無 |
| 輸入： | CML，LVDS，LVPECL |
| 輸出： | CML |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 10GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 1.71 V ~ 2.625 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 16-QFN（3x3） |
| 包裝： | 帶卷 (TR) |
Semiconductor Components Industries, LLC, 2010
August, 2010 Rev. 5
1
Publication Order Number:
NB7V32M/D
NB7V32M
1.8V / 2.5V, 10GHz ÷2 Clock
Divider with CML Outputs
MultiLevel Inputs w/ Internal
Termination
Description
The NB7V32M is a differential
B2 Clock divider with
asynchronous reset. The differential Clock inputs incorporate internal
50
W termination resistors and will accept LVPECL, CML and LVDS
logic levels.
The NB7V32M produces a
B2 output copy of an input Clock
operating up to 10 GHz with minimal jitter.
The RESET Pin is asserted on the rising edge. Upon powerup, the
internal flipflops will attain a random state; the Reset allows for the
synchronization of multiple NB7V32M’s in a system.
The 16 mA differential CML output provides matching internal
50
W termination which guarantees 400 mV output swing when
externally receiver terminated with 50
W to VCC .
The NB7V32M is the 1.8 V/2.5 V version of the NB7L32M
(2.5 V/3.3 V) and is offered in a low profile 3 mm x 3 mm 16pin
QFN package. The NB7V32M is a member of the GigaComm
family of high performance clock products. Application notes,
models, and support documentation are available at
www.onsemi.com.
Features
Maximum Input Clock Frequency > 10 GHz, typical
Random Clock Jitter < 0.8 ps RMS
200 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV PeaktoPeak, Typical
Operating Range: VCC = 1.71 V to 2.625 V with GND = 0 V
Internal 50 W Input Termination Resistors
QFN16 Package, 3 mm x 3 mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
1
NB7V
32M
ALYWG
G
16
1
Figure 1. Simplified Logic Diagram
Q
RESET
B2
50W
CLK
VTCLK
CLK
VTCLK
VREFAC
R
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