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參數資料
型號: NB7V52MMNTXG
廠商: ON Semiconductor
文件頁數: 1/10頁
文件大小: 0K
描述: IC FLIP FLOP DIFF RST/CML 16-QFN
標準包裝: 3,000
功能: 復位
類型: D 型
輸出類型: 差分
元件數: 1
每個元件的位元數: 1
延遲時間 - 傳輸: 300ps
觸發器類型: 負邊沿
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
包裝: 帶卷 (TR)
Semiconductor Components Industries, LLC, 2009
September, 2009 Rev. 3
1
Publication Order Number:
NB7V52M/D
NB7V52M
1.8V / 2.5V Differential D
Flip-Flop w/ Reset and CML
Outputs
MultiLevel Inputs w/ Internal Termination
Description
The NB7V52M is a 10 GHz differential D flipflop with a
differential asynchronous Reset. The differential D/D, CLK/CLK and
R/R inputs incorporate dual internal 50
W termination resistors and
will accept LVPECL, CML, LVDS logic levels.
When Clock transitions from logic Low to High, Data will be
transferred to the differential CML outputs. The differential Clock
inputs allow the NB7V52M to also be used as a negative edge
triggered device.
The 16 mA differential CML outputs provide matching internal
50
W termination and produce 400 mV output swings when externally
receiver terminated with a 50
W resistor to VCC.
The NB7V52M is offered in a low profile 3 mm x 3 mm 16pin
QFN package. The NB7V52M is a member of the GigaComm
family of high performance clock products. Application notes,
model s, and support document at i o n are avai l a bl e at
www.onsemi.com.
Features
Maximum Input Clock Frequency > 10 GHz
Maximum Input Data Rate > 10 Gb/s
Random Clock Jitter < 0.8 ps RMS, Max
200 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Differential CML Outputs, 400 mV PeaktoPeak, Typical
Operating Range: VCC = 1.71 V to 2.625 V with VEE = 0 V
Internal 50 W Input Termination Resistors
QFN16 Package, 3mm x 3mm
40°C to +85°C Ambient Operating Temperature
These are PbFree Devices
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
QFN16
MN SUFFIX
CASE 485G
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
1
NB7V
52M
ALYWG
G
16
1
Figure 1. Logic Diagram
Q
RESET
D FlipFlop
CLK
VTCLK
D
VTD
R
D
VTD
CLK
VTCLK
R
VTR
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