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參數(shù)資料
型號(hào): NBSG16MMNG
廠商: ON Semiconductor
文件頁(yè)數(shù): 1/11頁(yè)
文件大小: 0K
描述: IC RCVR/DVR RSECL SIGE DF 16QFN
標(biāo)準(zhǔn)包裝: 123
類型: 收發(fā)器
應(yīng)用: 儀表
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 16-QFN(3x3)
包裝: 管件
其它名稱: NBSG16MMNGOS
Semiconductor Components Industries, LLC, 2009
March, 2009 Rev. 7
1
Publication Order Number:
NBSG16M/D
NBSG16M
2.5 V/3.3 VMultilevel Input
to CML Clock/Data
Receiver/Driver/Translator
Buffer
Description
The NBSG16M is a differential current mode logic (CML)
receiver/driver/translator buffer. The device is functionally equivalent
to the EP16, LVEP16, or SG16 devices with CML output structure and
lower EMI capabilities.
Inputs incorporate internal 50
W termination resistors and accept
LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL,
LVCMOS, CML, or LVDS. The CML output structure contains
internal 50
W source termination resistor to VCC. The device
generates 400 mV output amplitude with 50
W receiver resistor to
VCC.
The VBB pin is internally generated voltage supply available to this
device only. For all singleended input conditions, the unused
complementary differential input is connected to VBB as a switching
reference voltage. VBB may also rebias AC coupled inputs. When
used, decouple VBB via a 0.01 mF capacitor and limit current sourcing
or sinking to 0.5 mA. When not used, VBB output should be left open.
Features
Maximum Input Clock Frequency > 10 GHz Typical
Maximum Input Data Rate > 10 Gb/s Typical
120 ps Typical Propagation Delay
35 ps Typical Rise and Fall Times
Positive CML Output with Operating Range:
VCC = 2.375 V to 3.465 V with VEE = 0 V
Negative CML Output with RSNECL or NECL Inputs with
Operating Range: VCC = 0 V with VEE = 2.375 V to 3.465 V
CML Output Level; 400 mV PeaktoPeak Output with
50
W Receiver Resistor to VCC
50 W Internal Input and Output Termination Resistors
Compatible with Existing 2.5 V/3.3 V LVEP, EP, LVEL
and SG Devices
VBB Reference Voltage Output
PbFree Packages are Available
*For additional marking information, refer to
Application Note AND8002/D.
MARKING
DIAGRAM*
http://onsemi.com
QFN16
MN SUFFIX
CASE 485G
1
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
16
SG
16M
ALYW G
G
1
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